Fix armle stagers
parent
b43a221959
commit
4e8092aceb
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@ -33,7 +33,7 @@ module Metasploit3
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{
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'Offsets' =>
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{
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'LPORT' => [ 226, 'n' ],
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'LPORT' => [ 214, 'n' ],
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},
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'Payload' =>
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[
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@ -110,8 +110,6 @@ module Metasploit3
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# Transmit our intermediate stager
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conn.put( [ payload.length ].pack(address_format) )
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Rex::ThreadSafe.sleep(0.5)
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return true
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end
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@ -103,8 +103,6 @@ def handle_intermediate_stage(conn, payload)
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# Transmit our intermediate stager
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conn.put( [ payload.length ].pack(address_format) )
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Rex::ThreadSafe.sleep(0.5)
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return true
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end
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