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[lantiq] cleanup patches 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32953 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
John Crispin 2012-08-03 08:53:02 +00:00
parent a8facfad2a
commit ce06d1cf7b
209 changed files with 146978 additions and 82080 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
target/linux/lantiq/files/arch/mips/configs/ase_defconfig Normal file
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@ -0,0 +1,67 @@
CONFIG_LANTIQ=y
CONFIG_SOC_AMAZON_SE=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_EXPERIMENTAL=y
CONFIG_DEFAULT_HOSTNAME="amazon_se"
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
CONFIG_INITRAMFS_ROOT_UID=1000
CONFIG_INITRAMFS_ROOT_GID=1000
+# CONFIG_RD_GZIP is not set
CONFIG_RD_LZMA=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_DEFAULT_DEADLINE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_ARPD=y
CONFIG_SYN_COOKIES=y
CONFIG_NETFILTER=y
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=y
CONFIG_NET_SCHED=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_LANTIQ=y
CONFIG_MISC_DEVICES=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_LANTIQ_ETOP=y
CONFIG_PHYLIB=y
CONFIG_SERIAL_LANTIQ=y
CONFIG_PINCTRL=y
CONFIG_GPIO_SYSFS=y
CONFIG_WATCHDOG=y
CONFIG_LANTIQ_WDT=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_XZ=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y

72
target/linux/lantiq/files/arch/mips/configs/falcon_defconfig Normal file
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@ -0,0 +1,72 @@
CONFIG_LANTIQ=y
CONFIG_SOC_FALCON=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_EXPERIMENTAL=y
CONFIG_DEFAULT_HOSTNAME="falcon"
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
CONFIG_INITRAMFS_ROOT_UID=1000
CONFIG_INITRAMFS_ROOT_GID=1000
+# CONFIG_RD_GZIP is not set
CONFIG_RD_LZMA=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_DEFAULT_DEADLINE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_ARPD=y
CONFIG_SYN_COOKIES=y
CONFIG_NETFILTER=y
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=y
CONFIG_NET_SCHED=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_LANTIQ=y
CONFIG_MTD_M25P80=y
CONFIG_MISC_DEVICES=y
CONFIG_EEPROM_AT24=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_PHYLIB=y
CONFIG_SERIAL_LANTIQ=y
CONFIG_I2C=y
CONFIG_I2C_FALCON=y
CONFIG_SPI=y
CONFIG_SPI_FALCON=y
CONFIG_PINCTRL=y
CONFIG_GPIO_SYSFS=y
CONFIG_WATCHDOG=y
CONFIG_LANTIQ_WDT=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_XZ=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y

66
target/linux/lantiq/files/arch/mips/configs/xway_defconfig Normal file
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@ -0,0 +1,66 @@
CONFIG_LANTIQ=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_EXPERIMENTAL=y
CONFIG_DEFAULT_HOSTNAME="danube"
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
CONFIG_INITRAMFS_ROOT_UID=1000
CONFIG_INITRAMFS_ROOT_GID=1000
# CONFIG_RD_GZIP is not set
CONFIG_RD_LZMA=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_DEFAULT_DEADLINE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_ARPD=y
CONFIG_SYN_COOKIES=y
CONFIG_NETFILTER=y
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=y
CONFIG_NET_SCHED=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_LANTIQ=y
CONFIG_MISC_DEVICES=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_LANTIQ_ETOP=y
CONFIG_PHYLIB=y
CONFIG_SERIAL_LANTIQ=y
CONFIG_PINCTRL=y
CONFIG_GPIO_SYSFS=y
CONFIG_WATCHDOG=y
CONFIG_LANTIQ_WDT=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_XZ=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y

25
target/linux/lantiq/files/arch/mips/include/asm/clkdev.h Normal file
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@ -0,0 +1,25 @@
/*
* based on arch/arm/include/asm/clkdev.h
*
* Copyright (C) 2008 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Helper for the clk API to assist looking up a struct clk.
*/
#ifndef __ASM_CLKDEV_H
#define __ASM_CLKDEV_H
#include <linux/slab.h>
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
{
return kzalloc(size, GFP_KERNEL);
}
#endif

268
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h Normal file
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@ -0,0 +1,268 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
*/
#ifndef _FALCON_IRQ__
#define _FALCON_IRQ__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define MIPS_CPU_TIMER_IRQ 7
/* HOST IF Event Interrupt */
#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0)
/* HOST IF Mailbox0 Receive Interrupt */
#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1)
/* HOST IF Mailbox0 Transmit Interrupt */
#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2)
/* HOST IF Mailbox1 Receive Interrupt */
#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3)
/* HOST IF Mailbox1 Transmit Interrupt */
#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4)
/* I2C Last Single Data Transfer Request */
#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8)
/* I2C Single Data Transfer Request */
#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9)
/* I2C Last Burst Data Transfer Request */
#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10)
/* I2C Burst Data Transfer Request */
#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11)
/* I2C Error Interrupt */
#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12)
/* I2C Protocol Interrupt */
#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13)
/* SSC Transmit Interrupt */
#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14)
/* SSC Receive Interrupt */
#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15)
/* SSC Error Interrupt */
#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16)
/* SSC Frame Interrupt */
#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17)
/* Advanced Encryption Standard Interrupt */
#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27)
/* Secure Hash Algorithm Interrupt */
#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28)
/* PCM Receive Interrupt */
#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29)
/* PCM Transmit Interrupt */
#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30)
/* PCM Transmit Crash Interrupt */
#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31)
/* EBU Serial Flash Command Error */
#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0)
/* EBU Serial Flash Command Overwrite Error */
#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1)
/* EBU Serial Flash Busy */
#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2)
/* External Interrupt from GPIO P0 */
#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4)
/* External Interrupt from GPIO P1 */
#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5)
/* External Interrupt from GPIO P2 */
#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6)
/* External Interrupt from GPIO P3 */
#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7)
/* External Interrupt from GPIO P4 */
#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8)
/* 8kHz backup interrupt derived from core-PLL */
#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10)
/* FSC Timer Interrupt 0 */
#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11)
/* FSC Timer Interrupt 1 */
#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12)
/* 8kHz root interrupt derived from GPON interface */
#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13)
/* Time of Day */
#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14)
/* PMA Interrupt from IntNode of the 200MHz Domain */
#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15)
/* PMA Interrupt from IntNode of the TX Clk Domain */
#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16)
/* PMA Interrupt from IntNode of the RX Clk Domain */
#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17)
/* SYS1 Interrupt */
#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20)
/* SYS GPE Interrupt */
#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21)
/* Watchdog Access Error Interrupt */
#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24)
/* Watchdog Prewarning Interrupt */
#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25)
/* SBIU interrupt */
#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27)
/* FPI Bus Control Unit Interrupt */
#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29)
/* DDR Controller Interrupt */
#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30)
/* Crossbar Error Interrupt */
#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31)
/* ICTRLL 0 Interrupt */
#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0)
/* ICTRLL 1 Interrupt */
#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1)
/* ICTRLL 2 Interrupt */
#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2)
/* ICTRLL 3 Interrupt */
#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3)
/* OCTRLL 0 Interrupt */
#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4)
/* OCTRLL 1 Interrupt */
#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5)
/* OCTRLL 2 Interrupt */
#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6)
/* OCTRLL 3 Interrupt */
#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7)
/* OCTRLG Interrupt */
#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9)
/* IQM Interrupt */
#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10)
/* FSQM Interrupt */
#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11)
/* TMU Interrupt */
#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12)
/* LINK1 Interrupt */
#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14)
/* ICTRLC 0 Interrupt */
#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16)
/* ICTRLC 1 Interrupt */
#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17)
/* OCTRLC Interrupt */
#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18)
/* CONFIG Break Interrupt */
#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19)
/* CONFIG Interrupt */
#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20)
/* Dispatcher Interrupt */
#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21)
/* TBM Interrupt */
#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22)
/* GTC Downstream Interrupt */
#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29)
/* GTC Upstream Interrupt */
#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30)
/* EIM Interrupt */
#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31)
/* ASC0 Transmit Interrupt */
#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0)
/* ASC0 Receive Interrupt */
#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1)
/* ASC0 Error Interrupt */
#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2)
/* ASC0 Transmit Buffer Interrupt */
#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3)
/* ASC0 Autobaud Start Interrupt */
#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4)
/* ASC0 Autobaud Detection Interrupt */
#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5)
/* ASC1 Modem Status Interrupt */
#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6)
/* ASC0 Soft Flow Control Interrupt */
#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7)
/* ASC1 Transmit Interrupt */
#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8)
/* ASC1 Receive Interrupt */
#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9)
/* ASC1 Error Interrupt */
#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10)
/* ASC1 Transmit Buffer Interrupt */
#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11)
/* ASC1 Autobaud Start Interrupt */
#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12)
/* ASC1 Autobaud Detection Interrupt */
#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13)
/* ASC1 Modem Status Interrupt */
#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14)
/* ASC1 Soft Flow Control Interrupt */
#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15)
/* GPTC Timer/Counter 1A Interrupt */
#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16)
/* GPTC Timer/Counter 1B Interrupt */
#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17)
/* GPTC Timer/Counter 2A Interrupt */
#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18)
/* GPTC Timer/Counter 2B Interrupt */
#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19)
/* GPTC Timer/Counter 3A Interrupt */
#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20)
/* GPTC Timer/Counter 3B Interrupt */
#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21)
/* DFEV0, Channel 1 Transmit Interrupt */
#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26)
/* DFEV0, Channel 1 Receive Interrupt */
#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27)
/* DFEV0, Channel 1 General Purpose Interrupt */
#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28)
/* DFEV0, Channel 0 Transmit Interrupt */
#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29)
/* DFEV0, Channel 0 Receive Interrupt */
#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30)
/* DFEV0, Channel 0 General Purpose Interrupt */
#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31)
/* ICTRLL 0 Error */
#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0)
/* ICTRLL 1 Error */
#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1)
/* ICTRLL 2 Error */
#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2)
/* ICTRLL 3 Error */
#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3)
/* OCTRLL 0 Error */
#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4)
/* OCTRLL 1 Error */
#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5)
/* OCTRLL 2 Error */
#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6)
/* OCTRLL 3 Error */
#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7)
/* ICTRLG Error */
#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8)
/* OCTRLG Error */
#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9)
/* IQM Error */
#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10)
/* FSQM Error */
#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11)
/* TMU Error */
#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12)
/* MPS Status Interrupt #0 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14)
/* MPS Status Interrupt #1 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15)
/* MPS Status Interrupt #2 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16)
/* MPS Status Interrupt #3 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17)
/* MPS Status Interrupt #4 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18)
/* MPS Status Interrupt #5 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19)
/* MPS Status Interrupt #6 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20)
/* MPS Status Interrupt #7 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21)
/* MPS Status Interrupt #8 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22)
/* VPE0 Exception Level Flag Interrupt */
#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29)
/* VPE0 Error Level Flag Interrupt */
#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30)
/* VPE0 Performance Monitoring Counter Interrupt */
#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31)
#endif /* _FALCON_IRQ__ */

18
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
*/
#ifndef __FALCON_IRQ_H
#define __FALCON_IRQ_H
#include <falcon_irq.h>
#define NR_IRQS 328
#include_next <irq.h>
#endif

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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#ifndef _LTQ_FALCON_H__
#define _LTQ_FALCON_H__
#ifdef CONFIG_SOC_FALCON
#include <lantiq.h>
/* Chip IDs */
#define SOC_ID_FALCON 0x01B8
/* SoC Types */
#define SOC_TYPE_FALCON 0x01
/* ASC0/1 - serial port */
#define LTQ_ASC0_BASE_ADDR 0x1E100C00
#define LTQ_ASC1_BASE_ADDR 0x1E100B00
#define LTQ_ASC_SIZE 0x100
#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
/*
* during early_printk no ioremap possible at this early stage
* lets use KSEG1 instead
*/
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
/* ICU - interrupt control unit */
#define LTQ_ICU_BASE_ADDR 0x1F880200
#define LTQ_ICU_SIZE 0x100
/* WDT */
#define LTQ_WDT_BASE_ADDR 0x1F8803F0
#define LTQ_WDT_SIZE 0x10
#define LTQ_RST_CAUSE_WDTRST 0x0002
/* EBU - external bus unit */
#define LTQ_EBU_BASE_ADDR 0x18000000
#define LTQ_EBU_SIZE 0x0100
#define LTQ_EBU_MODCON 0x000C
/* GPIO */
#define LTQ_GPIO0_BASE_ADDR 0x1D810000
#define LTQ_GPIO0_SIZE 0x0080
#define LTQ_GPIO1_BASE_ADDR 0x1E800100
#define LTQ_GPIO1_SIZE 0x0080
#define LTQ_GPIO2_BASE_ADDR 0x1D810100
#define LTQ_GPIO2_SIZE 0x0080
#define LTQ_GPIO3_BASE_ADDR 0x1E800200
#define LTQ_GPIO3_SIZE 0x0080
#define LTQ_GPIO4_BASE_ADDR 0x1E800300
#define LTQ_GPIO4_SIZE 0x0080
#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000
#define LTQ_PADCTRL0_SIZE 0x0100
#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400
#define LTQ_PADCTRL1_SIZE 0x0100
#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000
#define LTQ_PADCTRL2_SIZE 0x0100
#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500
#define LTQ_PADCTRL3_SIZE 0x0100
#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600
#define LTQ_PADCTRL4_SIZE 0x0100
/* I2C */
#define GPON_I2C_BASE 0x1E200000
#define GPON_I2C_SIZE 0x00010000
/* CHIP ID */
#define LTQ_STATUS_BASE_ADDR 0x1E802000
#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
#define LTQ_SYS1_BASE_ADDR 0x1EF00000
#define LTQ_SYS1_SIZE 0x0100
#define LTQ_STATUS_BASE_ADDR 0x1E802000
#define LTQ_STATUS_SIZE 0x0080
#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000
#define LTQ_SYS_ETH_SIZE 0x0100
#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000
#define LTQ_SYS_GPE_SIZE 0x0100
#define SYSCTL_SYS1 0
#define SYSCTL_SYSETH 1
#define SYSCTL_SYSGPE 2
/* Activation Status Register */
#define ACTS_ASC1_ACT 0x00000800
#define ACTS_I2C_ACT 0x00004000
#define ACTS_P0 0x00010000
#define ACTS_P1 0x00010000
#define ACTS_P2 0x00020000
#define ACTS_P3 0x00020000
#define ACTS_P4 0x00040000
#define ACTS_PADCTRL0 0x00100000
#define ACTS_PADCTRL1 0x00100000
#define ACTS_PADCTRL2 0x00200000
#define ACTS_PADCTRL3 0x00200000
#define ACTS_PADCTRL4 0x00400000
#define ACTS_I2C_ACT 0x00004000
/* global register ranges */
extern __iomem void *ltq_ebu_membase;
extern __iomem void *ltq_sys1_membase;
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
#define ltq_ebu_w32_mask(clear, set, reg) \
ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
#define ltq_sys1_w32_mask(clear, set, reg) \
ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
/* gpio wrapper to help configure the pin muxing */
extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
/* to keep the irq code generic we need to define these to 0 as falcon
has no EIU/EBU */
#define LTQ_EIU_BASE_ADDR 0
#define LTQ_EBU_PCC_ISTAT 0
static inline int ltq_is_ar9(void)
{
return 0;
}
static inline int ltq_is_vr9(void)
{
return 0;
}
static inline int ltq_is_falcon(void)
{
return 1;
}
#endif /* CONFIG_SOC_FALCON */
#endif /* _LTQ_XWAY_H__ */

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#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
/******************************************************************************
Copyright (c) 2002, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
******************************************************************************/
/*
* ####################################
* Definition
* ####################################
*/
/*
* Available Timer/Counter Index
*/
#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
#define TIMER_ANY 0x00
#define TIMER1A TIMER(1, 0)
#define TIMER1B TIMER(1, 1)
#define TIMER2A TIMER(2, 0)
#define TIMER2B TIMER(2, 1)
#define TIMER3A TIMER(3, 0)
#define TIMER3B TIMER(3, 1)
/*
* Flag of Timer/Counter
* These flags specify the way in which timer is configured.
*/
/* Bit size of timer/counter. */
#define TIMER_FLAG_16BIT 0x0000
#define TIMER_FLAG_32BIT 0x0001
/* Switch between timer and counter. */
#define TIMER_FLAG_TIMER 0x0000
#define TIMER_FLAG_COUNTER 0x0002
/* Stop or continue when overflowing/underflowing. */
#define TIMER_FLAG_ONCE 0x0000
#define TIMER_FLAG_CYCLIC 0x0004
/* Count up or counter down. */
#define TIMER_FLAG_UP 0x0000
#define TIMER_FLAG_DOWN 0x0008
/* Count on specific level or edge. */
#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
#define TIMER_FLAG_RISE_EDGE 0x0010
#define TIMER_FLAG_FALL_EDGE 0x0020
#define TIMER_FLAG_ANY_EDGE 0x0030
/* Signal is syncronous to module clock or not. */
#define TIMER_FLAG_UNSYNC 0x0000
#define TIMER_FLAG_SYNC 0x0080
/* Different interrupt handle type. */
#define TIMER_FLAG_NO_HANDLE 0x0000
#if defined(__KERNEL__)
#define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
#endif // defined(__KERNEL__)
#define TIMER_FLAG_SIGNAL 0x0300
/* Internal clock source or external clock source */
#define TIMER_FLAG_INT_SRC 0x0000
#define TIMER_FLAG_EXT_SRC 0x1000
/*
* ioctl Command
*/
#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
/*
* Data Type Used to Call ioctl
*/
struct gptu_ioctl_param {
unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
* GPTU_SET_COUNTER, this field is ID of expected *
* timer/counter. If it's zero, a timer/counter would *
* be dynamically allocated and ID would be stored in *
* this field. *
* In command GPTU_GET_COUNT_VALUE, this field is *
* ignored. *
* In other command, this field is ID of timer/counter *
* allocated. */
unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
* GPTU_SET_COUNTER, this field contains flags to *
* specify how to configure timer/counter. *
* In command GPTU_START_TIMER, zero indicate start *
* and non-zero indicate resume timer/counter. *
* In other command, this field is ignored. */
unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
* init/reload value. *
* In command GPTU_SET_TIMER, this field contains *
* frequency (0.001Hz) of timer. *
* In command GPTU_GET_COUNT_VALUE, current count *
* value would be stored in this field. *
* In command GPTU_CALCULATE_DIVIDER, this field *
* contains frequency wanted, and after calculation, *
* divider would be stored in this field to overwrite *
* the frequency. *
* In other command, this field is ignored. */
int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
* if signal is required, this field contains process *
* ID to which signal would be sent. *
* In other command, this field is ignored. */
int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
* if signal is required, this field contains signal *
* number which would be sent. *
* In other command, this field is ignored. */
};
/*
* ####################################
* Data Type
* ####################################
*/
typedef void (*timer_callback)(unsigned long arg);
extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
extern int lq_free_timer(unsigned int);
extern int lq_start_timer(unsigned int, int);
extern int lq_stop_timer(unsigned int);
extern int lq_reset_counter_flags(u32 timer, u32 flags);
extern int lq_get_count_value(unsigned int, unsigned long *);
extern u32 lq_cal_divider(unsigned long);
extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
extern int lq_set_counter(unsigned int timer, unsigned int flag,
u32 reload, unsigned long arg1, unsigned long arg2);
#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */

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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __BASE_REG_H
#define __BASE_REG_H
#ifndef KSEG1
#define KSEG1 0xA0000000
#endif
#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000)
#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000)
#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000)
#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000)
#define LTQ_ASC0_BASE (KSEG1 + 0x14100100)
#define LTQ_ASC1_BASE (KSEG1 + 0x14100200)
#define LTQ_SSC0_BASE (0x14100300)
#define LTQ_SSC1_BASE (0x14100400)
#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600)
#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100)
#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800)
#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900)
#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400)
#define LTQ_EBU_BASE (KSEG1 + 0x14102000)
#define LTQ_DMA_BASE (KSEG1 + 0x14104000)
#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000)
#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000)
#define LTQ_ES_BASE (KSEG1 + 0x18000000)
#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000)
#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800)
#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000)
#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000)
#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100)
#define LTQ_MBS_BASE (KSEG1 + 0x1E000200)
#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500)
#endif

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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __BOOT_REG_H
#define __BOOT_REG_H
#define LTQ_BOOT_CPU_OFFSET 0x20
#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x00)
#define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x04)
#define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x08)
#define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C)
#define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x10)
#define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x14)
#define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */
#define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */
#define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C)
#endif

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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __DMA_REG_H
#define __DMA_REG_H
#define dma_r32(reg) ltq_r32(&dma->reg)
#define dma_w32(val, reg) ltq_w32(val, &dma->reg)
#define dma_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &dma->reg)
/** DMA register structure */
struct svip_reg_dma {
volatile unsigned long clc; /* 0x00 */
volatile unsigned long reserved0; /* 0x04 */
volatile unsigned long id; /* 0x08 */
volatile unsigned long reserved1; /* 0x0c */
volatile unsigned long ctrl; /* 0x10 */
volatile unsigned long cpoll; /* 0x14 */
volatile unsigned long cs; /* 0x18 */
volatile unsigned long cctrl; /* 0x1C */
volatile unsigned long cdba; /* 0x20 */
volatile unsigned long cdlen; /* 0x24 */
volatile unsigned long cis; /* 0x28 */
volatile unsigned long cie; /* 0x2C */
volatile unsigned long cgbl; /* 0x30 */
volatile unsigned long reserved2[3]; /* 0x34 */
volatile unsigned long ps; /* 0x40 */
volatile unsigned long pctrl; /* 0x44 */
volatile unsigned long reserved3[43]; /* 0x48 */
volatile unsigned long irnen; /* 0xF4 */
volatile unsigned long irncr; /* 0xF8 */
volatile unsigned long irnicr; /* 0xFC */
};
/*******************************************************************************
* CLC Register
******************************************************************************/
/* Fast Shut-Off Enable Bit (5) */
#define DMA_CLC_FSOE (0x1 << 5)
#define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5)
#define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1)
#define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5))
/* Suspend Bit Write Enable for OCDS (4) */
#define DMA_CLC_SBWE (0x1 << 4)
#define DMA_CLC_SBWE_VAL(val) (((val) & 0x1) << 4)
#define DMA_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~DMA_CLC_SBWE) | (val) & 1) << 4)
/* External Request Disable (3) */
#define DMA_CLC_EDIS (0x1 << 3)
#define DMA_CLC_EDIS_VAL(val) (((val) & 0x1) << 3)
#define DMA_CLC_EDIS_GET(val) ((((val) & DMA_CLC_EDIS) >> 3) & 0x1)
#define DMA_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~DMA_CLC_EDIS) | (((val) & 0x1) << 3))
/* Suspend Enable Bit for OCDS (2) */
#define DMA_CLC_SPEN (0x1 << 2)
#define DMA_CLC_SPEN_VAL(val) (((val) & 0x1) << 2)
#define DMA_CLC_SPEN_GET(val) ((((val) & DMA_CLC_SPEN) >> 2) & 0x1)
#define DMA_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~DMA_CLC_SPEN) | (((val) & 0x1) << 2))
/* Disable Status Bit (1) */
#define DMA_CLC_DISS (0x1 << 1)
#define DMA_CLC_DISS_GET(val) ((((val) & DMA_CLC_DISS) >> 1) & 0x1)
/* Disable Request Bit (0) */
#define DMA_CLC_DISR (0x1)
#define DMA_CLC_DISR_VAL(val) (((val) & 0x1) << 0)
#define DMA_CLC_DISR_GET(val) ((((val) & DMA_CLC_DISR) >> 0) & 0x1)
#define DMA_CLC_DISR_SET(reg,val) (reg) = ((reg & ~DMA_CLC_DISR) | (((val) & 0x1) << 0))
/*******************************************************************************
* ID Register
******************************************************************************/
/* Number of Channels (25:20) */
#define DMA_ID_CHNR (0x3f << 20)
#define DMA_ID_CHNR_GET(val) ((((val) & DMA_ID_CHNR) >> 20) & 0x3f)
/* Number of Ports (19:16) */
#define DMA_ID_PRTNR (0xf << 16)
#define DMA_ID_PRTNR_GET(val) ((((val) & DMA_ID_PRTNR) >> 16) & 0xf)
/* Module ID (15:8) */
#define DMA_ID_ID (0xff << 8)
#define DMA_ID_ID_GET(val) ((((val) & DMA_ID_ID) >> 8) & 0xff)
/* Revision (4:0) */
#define DMA_ID_REV (0x1f)
#define DMA_ID_REV_GET(val) ((((val) & DMA_ID_REV) >> 0) & 0x1f)
/*******************************************************************************
* Control Register
******************************************************************************/
/* Global Software Reset (0) */
#define DMA_CTRL_RST (0x1)
#define DMA_CTRL_RST_GET(val) ((((val) & DMA_CTRL_RST) >> 0) & 0x1)
/*******************************************************************************
* Channel Polling Register
******************************************************************************/
/* Enable (31) */
#define DMA_CPOLL_EN (0x1 << 31)
#define DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31)
#define DMA_CPOLL_EN_GET(val) ((((val) & DMA_CPOLL_EN) >> 31) & 0x1)
#define DMA_CPOLL_EN_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_EN) | (((val) & 0x1) << 31))
/* Counter (15:4) */
#define DMA_CPOLL_CNT (0xfff << 4)
#define DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4)
#define DMA_CPOLL_CNT_GET(val) ((((val) & DMA_CPOLL_CNT) >> 4) & 0xfff)
#define DMA_CPOLL_CNT_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_CNT) | (((val) & 0xfff) << 4))
/*******************************************************************************
* Global Buffer Length Register
******************************************************************************/
/* Global Buffer Length (15:0) */
#define DMA_CGBL_GBL (0xffff)
#define DMA_CGBL_GBL_VAL(val) (((val) & 0xffff) << 0)
#define DMA_CGBL_GBL_GET(val) ((((val) & DMA_CGBL_GBL) >> 0) & 0xffff)
#define DMA_CGBL_GBL_SET(reg,val) (reg) = ((reg & ~DMA_CGBL_GBL) | (((val) & 0xffff) << 0))
/*******************************************************************************
* Channel Select Register
******************************************************************************/
/* Channel Selection (4:0) */
#define DMA_CS_CS (0x1f)
#define DMA_CS_CS_VAL(val) (((val) & 0x1f) << 0)
#define DMA_CS_CS_GET(val) ((((val) & DMA_CS_CS) >> 0) & 0x1f)
#define DMA_CS_CS_SET(reg,val) (reg) = ((reg & ~DMA_CS_CS) | (((val) & 0x1f) << 0))
/*******************************************************************************
* Channel Control Register
******************************************************************************/
/* Peripheral to Peripheral Copy (24) */
#define DMA_CCTRL_P2PCPY (0x1 << 24)
#define DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24)
#define DMA_CCTRL_P2PCPY_GET(val) ((((val) & DMA_CCTRL_P2PCPY) >> 24) & 0x1)
#define DMA_CCTRL_P2PCPY_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_P2PCPY) | (((val) & 0x1) << 24))
/* Channel Weight for Transmit Direction (17:16) */
#define DMA_CCTRL_TXWGT (0x3 << 16)
#define DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16)
#define DMA_CCTRL_TXWGT_GET(val) ((((val) & DMA_CCTRL_TXWGT) >> 16) & 0x3)
#define DMA_CCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_TXWGT) | (((val) & 0x3) << 16))
/* Port Assignment (13:11) */
#define DMA_CCTRL_PRTNR (0x7 << 11)
#define DMA_CCTRL_PRTNR_GET(val) ((((val) & DMA_CCTRL_PRTNR) >> 11) & 0x7)
/* Class (10:9) */
#define DMA_CCTRL_CLASS (0x3 << 9)
#define DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9)
#define DMA_CCTRL_CLASS_GET(val) ((((val) & DMA_CCTRL_CLASS) >> 9) & 0x3)
#define DMA_CCTRL_CLASS_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_CLASS) | (((val) & 0x3) << 9))
/* Direction (8) */
#define DMA_CCTRL_DIR (0x1 << 8)
#define DMA_CCTRL_DIR_GET(val) ((((val) & DMA_CCTRL_DIR) >> 8) & 0x1)
/* Reset (1) */
#define DMA_CCTRL_RST (0x1 << 1)
#define DMA_CCTRL_RST_VAL(val) (((val) & 0x1) << 1)
#define DMA_CCTRL_RST_GET(val) ((((val) & DMA_CCTRL_RST) >> 1) & 0x1)
#define DMA_CCTRL_RST_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_RST) | (((val) & 0x1) << 1))
/* Channel On or Off (0) */
#define DMA_CCTRL_ON_OFF (0x1)
#define DMA_CCTRL_ON_OFF_VAL(val) (((val) & 0x1) << 0)
#define DMA_CCTRL_ON_OFF_GET(val) ((((val) & DMA_CCTRL_ON_OFF) >> 0) & 0x1)
#define DMA_CCTRL_ON_OFF_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_ON_OFF) | (((val) & 0x1) << 0))
/*******************************************************************************
* Channel Descriptor Base Address Register
******************************************************************************/
/* Channel Descriptor Base Address (29:3) */
#define DMA_CDBA_CDBA (0x7ffffff << 3)
#define DMA_CDBA_CDBA_VAL(val) (((val) & 0x7ffffff) << 3)
#define DMA_CDBA_CDBA_GET(val) ((((val) & DMA_CDBA_CDBA) >> 3) & 0x7ffffff)
#define DMA_CDBA_CDBA_SET(reg,val) (reg) = ((reg & ~DMA_CDBA_CDBA) | (((val) & 0x7ffffff) << 3))
/*******************************************************************************
* Channel Descriptor Length Register
******************************************************************************/
/* Channel Descriptor Length (7:0) */
#define DMA_CDLEN_CDLEN (0xff)
#define DMA_CDLEN_CDLEN_VAL(val) (((val) & 0xff) << 0)
#define DMA_CDLEN_CDLEN_GET(val) ((((val) & DMA_CDLEN_CDLEN) >> 0) & 0xff)
#define DMA_CDLEN_CDLEN_SET(reg,val) (reg) = ((reg & ~DMA_CDLEN_CDLEN) | (((val) & 0xff) << 0))
/*******************************************************************************
* Channel Interrupt Status Register
******************************************************************************/
/* SAI Read Error Interrupt (5) */
#define DMA_CIS_RDERR (0x1 << 5)
#define DMA_CIS_RDERR_GET(val) ((((val) & DMA_CIS_RDERR) >> 5) & 0x1)
/* Channel Off Interrupt (4) */
#define DMA_CIS_CHOFF (0x1 << 4)
#define DMA_CIS_CHOFF_GET(val) ((((val) & DMA_CIS_CHOFF) >> 4) & 0x1)
/* Descriptor Complete Interrupt (3) */
#define DMA_CIS_DESCPT (0x1 << 3)
#define DMA_CIS_DESCPT_GET(val) ((((val) & DMA_CIS_DESCPT) >> 3) & 0x1)
/* Descriptor Under-Run Interrupt (2) */
#define DMA_CIS_DUR (0x1 << 2)
#define DMA_CIS_DUR_GET(val) ((((val) & DMA_CIS_DUR) >> 2) & 0x1)
/* End of Packet Interrupt (1) */
#define DMA_CIS_EOP (0x1 << 1)
#define DMA_CIS_EOP_GET(val) ((((val) & DMA_CIS_EOP) >> 1) & 0x1)
/*******************************************************************************
* Channel Interrupt Enable Register
******************************************************************************/
/* SAI Read Error Interrupt (5) */
#define DMA_CIE_RDERR (0x1 << 5)
#define DMA_CIE_RDERR_GET(val) ((((val) & DMA_CIE_RDERR) >> 5) & 0x1)
/* Channel Off Interrupt (4) */
#define DMA_CIE_CHOFF (0x1 << 4)
#define DMA_CIE_CHOFF_GET(val) ((((val) & DMA_CIE_CHOFF) >> 4) & 0x1)
/* Descriptor Complete Interrupt Enable (3) */
#define DMA_CIE_DESCPT (0x1 << 3)
#define DMA_CIE_DESCPT_GET(val) ((((val) & DMA_CIE_DESCPT) >> 3) & 0x1)
/* Descriptor Under Run Interrupt Enable (2) */
#define DMA_CIE_DUR (0x1 << 2)
#define DMA_CIE_DUR_GET(val) ((((val) & DMA_CIE_DUR) >> 2) & 0x1)
/* End of Packet Interrupt Enable (1) */
#define DMA_CIE_EOP (0x1 << 1)
#define DMA_CIE_EOP_GET(val) ((((val) & DMA_CIE_EOP) >> 1) & 0x1)
/*******************************************************************************
* Port Select Register
******************************************************************************/
/* Port Selection (2:0) */
#define DMA_PS_PS (0x7)
#define DMA_PS_PS_VAL(val) (((val) & 0x7) << 0)
#define DMA_PS_PS_GET(val) ((((val) & DMA_PS_PS) >> 0) & 0x7)
#define DMA_PS_PS_SET(reg,val) (reg) = ((reg & ~DMA_PS_PS) | (((val) & 0x7) << 0))
/*******************************************************************************
* Port Control Register
******************************************************************************/
/* General Purpose Control (16) */
#define DMA_PCTRL_GPC (0x1 << 16)
#define DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16)
#define DMA_PCTRL_GPC_GET(val) ((((val) & DMA_PCTRL_GPC) >> 16) & 0x1)
#define DMA_PCTRL_GPC_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_GPC) | (((val) & 0x1) << 16))
/* Port Weight for Transmit Direction (14:12) */
#define DMA_PCTRL_TXWGT (0x7 << 12)
#define DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12)
#define DMA_PCTRL_TXWGT_GET(val) ((((val) & DMA_PCTRL_TXWGT) >> 12) & 0x7)
#define DMA_PCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXWGT) | (((val) & 0x7) << 12))
/* Endianness for Transmit Direction (11:10) */
#define DMA_PCTRL_TXENDI (0x3 << 10)
#define DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10)
#define DMA_PCTRL_TXENDI_GET(val) ((((val) & DMA_PCTRL_TXENDI) >> 10) & 0x3)
#define DMA_PCTRL_TXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXENDI) | (((val) & 0x3) << 10))
/* Endianness for Receive Direction (9:8) */
#define DMA_PCTRL_RXENDI (0x3 << 8)
#define DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8)
#define DMA_PCTRL_RXENDI_GET(val) ((((val) & DMA_PCTRL_RXENDI) >> 8) & 0x3)
#define DMA_PCTRL_RXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXENDI) | (((val) & 0x3) << 8))
/* Packet Drop Enable (6) */
#define DMA_PCTRL_PDEN (0x1 << 6)
#define DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6)
#define DMA_PCTRL_PDEN_GET(val) ((((val) & DMA_PCTRL_PDEN) >> 6) & 0x1)
#define DMA_PCTRL_PDEN_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_PDEN) | (((val) & 0x1) << 6))
/* Burst Length for Transmit Direction (5:4) */
#define DMA_PCTRL_TXBL (0x3 << 4)
#define DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4)
#define DMA_PCTRL_TXBL_GET(val) ((((val) & DMA_PCTRL_TXBL) >> 4) & 0x3)
#define DMA_PCTRL_TXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXBL) | (((val) & 0x3) << 4))
/* Burst Length for Receive Direction (3:2) */
#define DMA_PCTRL_RXBL (0x3 << 2)
#define DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2)
#define DMA_PCTRL_RXBL_GET(val) ((((val) & DMA_PCTRL_RXBL) >> 2) & 0x3)
#define DMA_PCTRL_RXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXBL) | (((val) & 0x3) << 2))
/*******************************************************************************
* DMA_IRNEN Register
******************************************************************************/
/* Channel x Interrupt Request Enable (23) */
#define DMA_IRNEN_CH23 (0x1 << 23)
#define DMA_IRNEN_CH23_VAL(val) (((val) & 0x1) << 23)
#define DMA_IRNEN_CH23_GET(val) ((((val) & DMA_IRNEN_CH23) >> 23) & 0x1)
#define DMA_IRNEN_CH23_SET(reg,val) (reg) = ((reg & ~DMA_IRNEN_CH23) | (((val) & 0x1) << 23))
/*******************************************************************************
* DMA_IRNCR Register
******************************************************************************/
/* Channel x Interrupt (23) */
#define DMA_IRNCR_CH23 (0x1 << 23)
#define DMA_IRNCR_CH23_GET(val) ((((val) & DMA_IRNCR_CH23) >> 23) & 0x1)
/*******************************************************************************
* DMA_IRNICR Register
******************************************************************************/
/* Channel x Interrupt Request (23) */
#define DMA_IRNICR_CH23 (0x1 << 23)
#define DMA_IRNICR_CH23_GET(val) ((((val) & DMA_IRNICR_CH23) >> 23) & 0x1)
#endif

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target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h Normal file
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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __EBU_REG_H
#define __EBU_REG_H
#define ebu_r32(reg) ltq_r32(&ebu->reg)
#define ebu_w32(val, reg) ltq_w32(val, &ebu->reg)
#define ebu_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &ebu->reg)
/** EBU register structure */
struct svip_reg_ebu {
volatile unsigned long clc; /* 0x0000 */
volatile unsigned long reserved0; /* 0x04 */
volatile unsigned long id; /* 0x0008 */
volatile unsigned long reserved1; /* 0x0c */
volatile unsigned long con; /* 0x0010 */
volatile unsigned long reserved2[3]; /* 0x14 */
volatile unsigned long addr_sel_0; /* 0x0020 */
volatile unsigned long addr_sel_1; /* 0x0024 */
volatile unsigned long addr_sel_2; /* 0x0028 */
volatile unsigned long addr_sel_3; /* 0x002c */
volatile unsigned long reserved3[12]; /* 0x30 */
volatile unsigned long con_0; /* 0x0060 */
volatile unsigned long con_1; /* 0x0064 */
volatile unsigned long con_2; /* 0x0068 */
volatile unsigned long con_3; /* 0x006c */
volatile unsigned long reserved4[4]; /* 0x70 */
volatile unsigned long emu_addr; /* 0x0080 */
volatile unsigned long emu_bc; /* 0x0084 */
volatile unsigned long emu_con; /* 0x0088 */
volatile unsigned long reserved5; /* 0x8c */
volatile unsigned long pcc_con; /* 0x0090 */
volatile unsigned long pcc_stat; /* 0x0094 */
volatile unsigned long reserved6[2]; /* 0x98 */
volatile unsigned long pcc_istat; /* 0x00A0 */
volatile unsigned long pcc_ien; /* 0x00A4 */
volatile unsigned long pcc_int_out; /* 0x00A8 */
volatile unsigned long pcc_irs; /* 0x00AC */
volatile unsigned long nand_con; /* 0x00B0 */
volatile unsigned long nand_wait; /* 0x00B4 */
volatile unsigned long nand_ecc0; /* 0x00B8 */
volatile unsigned long nand_ecc_ac; /* 0x00BC */
};
/*******************************************************************************
* EBU
******************************************************************************/
#define LTQ_EBU_CLC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0000))
#define LTQ_EBU_ID ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0008))
#define LTQ_EBU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0010))
#define LTQ_EBU_ADDR_SEL_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0020))
#define LTQ_EBU_ADDR_SEL_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0024))
#define LTQ_EBU_ADDR_SEL_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0028))
#define LTQ_EBU_ADDR_SEL_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x002c))
#define LTQ_EBU_CON_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0060))
#define LTQ_EBU_CON_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0064))
#define LTQ_EBU_CON_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0068))
#define LTQ_EBU_CON_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x006c))
#define LTQ_EBU_EMU_BC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0084))
#define LTQ_EBU_PCC_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0090))
#define LTQ_EBU_PCC_STAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0094))
#define LTQ_EBU_PCC_ISTAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A0))
#define LTQ_EBU_PCC_IEN ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A4))
#define LTQ_EBU_PCC_INT_OUT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A8))
#define LTQ_EBU_PCC_IRS ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00AC))
#define LTQ_EBU_NAND_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B0))
#define LTQ_EBU_NAND_WAIT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B4))
#define LTQ_EBU_NAND_ECC0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B8))
#define LTQ_EBU_NAND_ECC_AC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00BC))
#define LTQ_EBU_EMU_ADDR ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0080))
#define LTQ_EBU_EMU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0088))
/*******************************************************************************
* EBU Clock Control Register
******************************************************************************/
/* EBU Disable Status Bit (1) */
#define LTQ_EBU_CLC_DISS (0x1 << 1)
#define LTQ_EBU_CLC_DISS_GET(val) ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1)
/* Used for Enable/disable Control of the EBU (0) */
#define LTQ_EBU_CLC_DISR (0x1)
#define LTQ_EBU_CLC_DISR_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_CLC_DISR_GET(val) ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1)
#define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val) & 0x1) << 0))
/*******************************************************************************
* EBU Identification Register (Internal)
******************************************************************************/
/* Module Number (31:8) */
#define LTQ_EBU_ID_MODNUM (0xffffff << 8)
#define LTQ_EBU_ID_MODNUM_GET(val) ((((val) & LTQ_EBU_ID_MODNUM) >> 8) & 0xffffff)
/* Revision Number (7:0) */
#define LTQ_EBU_ID_REVNUM (0xff)
#define LTQ_EBU_ID_REVNUM_GET(val) ((((val) & LTQ_EBU_ID_REVNUM) >> 0) & 0xff)
/*******************************************************************************
* External Bus Unit Control Register
******************************************************************************/
/* Driver Turn-Around Control, Chip Select Triggered (22:20) */
#define LTQ_EBU_CON_DTACS (0x7 << 20)
#define LTQ_EBU_CON_DTACS_VAL(val) (((val) & 0x7) << 20)
#define LTQ_EBU_CON_DTACS_GET(val) ((((val) & LTQ_EBU_CON_DTACS) >> 20) & 0x7)
#define LTQ_EBU_CON_DTACS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTACS) | (((val) & 0x7) << 20))
/* Driver Turn-Around Control, Read-write Triggered (18:16) */
#define LTQ_EBU_CON_DTARW (0x7 << 16)
#define LTQ_EBU_CON_DTARW_VAL(val) (((val) & 0x7) << 16)
#define LTQ_EBU_CON_DTARW_GET(val) ((((val) & LTQ_EBU_CON_DTARW) >> 16) & 0x7)
#define LTQ_EBU_CON_DTARW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTARW) | (((val) & 0x7) << 16))
/* Time-Out Control (15:8) */
#define LTQ_EBU_CON_TOUTC (0xff << 8)
#define LTQ_EBU_CON_TOUTC_VAL(val) (((val) & 0xff) << 8)
#define LTQ_EBU_CON_TOUTC_GET(val) ((((val) & LTQ_EBU_CON_TOUTC) >> 8) & 0xff)
#define LTQ_EBU_CON_TOUTC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_TOUTC) | (((val) & 0xff) << 8))
/* Arbitration Mode (7:6) */
#define LTQ_EBU_CON_ARBMODE (0x3 << 6)
#define LTQ_EBU_CON_ARBMODE_VAL(val) (((val) & 0x3) << 6)
#define LTQ_EBU_CON_ARBMODE_GET(val) ((((val) & LTQ_EBU_CON_ARBMODE) >> 6) & 0x3)
#define LTQ_EBU_CON_ARBMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBMODE) | (((val) & 0x3) << 6))
/* Arbitration Synchronization (5) */
#define LTQ_EBU_CON_ARBSYNC (0x1 << 5)
#define LTQ_EBU_CON_ARBSYNC_VAL(val) (((val) & 0x1) << 5)
#define LTQ_EBU_CON_ARBSYNC_GET(val) ((((val) & LTQ_EBU_CON_ARBSYNC) >> 5) & 0x1)
#define LTQ_EBU_CON_ARBSYNC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBSYNC) | (((val) & 0x1) << 5))
/*******************************************************************************
* Address Select Registers
******************************************************************************/
/* Memory Region Base Address (31:12) */
#define LTQ_EBU_ADDR_SEL_0_BASE (0xfffff << 12)
#define LTQ_EBU_ADDR_SEL_0_BASE_VAL(val) (((val) & 0xfffff) << 12)
#define LTQ_EBU_ADDR_SEL_0_BASE_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_BASE) >> 12) & 0xfffff)
#define LTQ_EBU_ADDR_SEL_0_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_BASE) | (((val) & 0xfffff) << 12))
/* Memory Region Address Mask (7:4) */
#define LTQ_EBU_ADDR_SEL_0_MASK (0xf << 4)
#define LTQ_EBU_ADDR_SEL_0_MASK_VAL(val) (((val) & 0xf) << 4)
#define LTQ_EBU_ADDR_SEL_0_MASK_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MASK) >> 4) & 0xf)
#define LTQ_EBU_ADDR_SEL_0_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MASK) | (((val) & 0xf) << 4))
/* Memory Region Mirror Enable Control (1) */
#define LTQ_EBU_ADDR_SEL_0_MRME (0x1 << 1)
#define LTQ_EBU_ADDR_SEL_0_MRME_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_ADDR_SEL_0_MRME_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MRME) >> 1) & 0x1)
#define LTQ_EBU_ADDR_SEL_0_MRME_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MRME) | (((val) & 0x1) << 1))
/* Memory Region Enable Control (0) */
#define LTQ_EBU_ADDR_SEL_0_REGEN (0x1)
#define LTQ_EBU_ADDR_SEL_0_REGEN_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_ADDR_SEL_0_REGEN_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_REGEN) >> 0) & 0x1)
#define LTQ_EBU_ADDR_SEL_0_REGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_REGEN) | (((val) & 0x1) << 0))
/*******************************************************************************
* Bus Configuration Registers
******************************************************************************/
/* Memory Region Write Protection (31) */
#define LTQ_EBU_CON_0_WRDIS (0x1 << 31)
#define LTQ_EBU_CON_0_WRDIS_VAL(val) (((val) & 0x1) << 31)
#define LTQ_EBU_CON_0_WRDIS_GET(val) ((((val) & LTQ_EBU_CON_0_WRDIS) >> 31) & 0x1)
#define LTQ_EBU_CON_0_WRDIS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WRDIS) | (((val) & 0x1) << 31))
/* Address Swapping (30) */
#define LTQ_EBU_CON_0_ADSWP (0x1 << 30)
#define LTQ_EBU_CON_0_ADSWP_VAL(val) (((val) & 0x1) << 30)
#define LTQ_EBU_CON_0_ADSWP_GET(val) ((((val) & LTQ_EBU_CON_0_ADSWP) >> 30) & 0x1)
#define LTQ_EBU_CON_0_ADSWP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ADSWP) | (((val) & 0x1) << 30))
/* Address Generation Control (26:24) */
#define LTQ_EBU_CON_0_AGEN (0x7 << 24)
#define LTQ_EBU_CON_0_AGEN_VAL(val) (((val) & 0x7) << 24)
#define LTQ_EBU_CON_0_AGEN_GET(val) ((((val) & LTQ_EBU_CON_0_AGEN) >> 24) & 0x7)
#define LTQ_EBU_CON_0_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_AGEN) | (((val) & 0x7) << 24))
/* Extended Address Setup Control (22) */
#define LTQ_EBU_CON_0_SETUP (0x1 << 22)
#define LTQ_EBU_CON_0_SETUP_VAL(val) (((val) & 0x1) << 22)
#define LTQ_EBU_CON_0_SETUP_GET(val) ((((val) & LTQ_EBU_CON_0_SETUP) >> 22) & 0x1)
#define LTQ_EBU_CON_0_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_SETUP) | (((val) & 0x1) << 22))
/* Variable Wait-State Insertion Control (21:20) */
#define LTQ_EBU_CON_0_WAIT (0x3 << 20)
#define LTQ_EBU_CON_0_WAIT_VAL(val) (((val) & 0x3) << 20)
#define LTQ_EBU_CON_0_WAIT_GET(val) ((((val) & LTQ_EBU_CON_0_WAIT) >> 20) & 0x3)
#define LTQ_EBU_CON_0_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAIT) | (((val) & 0x3) << 20))
/* Active WAIT Level Control (19) */
#define LTQ_EBU_CON_0_WINV (0x1 << 19)
#define LTQ_EBU_CON_0_WINV_VAL(val) (((val) & 0x1) << 19)
#define LTQ_EBU_CON_0_WINV_GET(val) ((((val) & LTQ_EBU_CON_0_WINV) >> 19) & 0x1)
#define LTQ_EBU_CON_0_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WINV) | (((val) & 0x1) << 19))
/* External Device Data Width Control (17:16) */
#define LTQ_EBU_CON_0_PW (0x3 << 16)
#define LTQ_EBU_CON_0_PW_VAL(val) (((val) & 0x3) << 16)
#define LTQ_EBU_CON_0_PW_GET(val) ((((val) & LTQ_EBU_CON_0_PW) >> 16) & 0x3)
#define LTQ_EBU_CON_0_PW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_PW) | (((val) & 0x3) << 16))
/* Address Latch Enable ALE Duration Control (15:14) */
#define LTQ_EBU_CON_0_ALEC (0x3 << 14)
#define LTQ_EBU_CON_0_ALEC_VAL(val) (((val) & 0x3) << 14)
#define LTQ_EBU_CON_0_ALEC_GET(val) ((((val) & LTQ_EBU_CON_0_ALEC) >> 14) & 0x3)
#define LTQ_EBU_CON_0_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ALEC) | (((val) & 0x3) << 14))
/* Byte Control Signal Timing Mode Control (13:12) */
#define LTQ_EBU_CON_0_BCGEN (0x3 << 12)
#define LTQ_EBU_CON_0_BCGEN_VAL(val) (((val) & 0x3) << 12)
#define LTQ_EBU_CON_0_BCGEN_GET(val) ((((val) & LTQ_EBU_CON_0_BCGEN) >> 12) & 0x3)
#define LTQ_EBU_CON_0_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_BCGEN) | (((val) & 0x3) << 12))
/* Write Access Wait-State Control (10:8) */
#define LTQ_EBU_CON_0_WAITWRC (0x7 << 8)
#define LTQ_EBU_CON_0_WAITWRC_VAL(val) (((val) & 0x7) << 8)
#define LTQ_EBU_CON_0_WAITWRC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITWRC) >> 8) & 0x7)
#define LTQ_EBU_CON_0_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITWRC) | (((val) & 0x7) << 8))
/* Read Access Wait-State Control (7:6) */
#define LTQ_EBU_CON_0_WAITRDC (0x3 << 6)
#define LTQ_EBU_CON_0_WAITRDC_VAL(val) (((val) & 0x3) << 6)
#define LTQ_EBU_CON_0_WAITRDC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITRDC) >> 6) & 0x3)
#define LTQ_EBU_CON_0_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITRDC) | (((val) & 0x3) << 6))
/* Hold/Pause Cycle Control (5:4) */
#define LTQ_EBU_CON_0_HOLDC (0x3 << 4)
#define LTQ_EBU_CON_0_HOLDC_VAL(val) (((val) & 0x3) << 4)
#define LTQ_EBU_CON_0_HOLDC_GET(val) ((((val) & LTQ_EBU_CON_0_HOLDC) >> 4) & 0x3)
#define LTQ_EBU_CON_0_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_HOLDC) | (((val) & 0x3) << 4))
/* Recovery Cycle Control (3:2) */
#define LTQ_EBU_CON_0_RECOVC (0x3 << 2)
#define LTQ_EBU_CON_0_RECOVC_VAL(val) (((val) & 0x3) << 2)
#define LTQ_EBU_CON_0_RECOVC_GET(val) ((((val) & LTQ_EBU_CON_0_RECOVC) >> 2) & 0x3)
#define LTQ_EBU_CON_0_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_RECOVC) | (((val) & 0x3) << 2))
/* Wait Cycle Multiplier Control (1:0) */
#define LTQ_EBU_CON_0_CMULT (0x3)
#define LTQ_EBU_CON_0_CMULT_VAL(val) (((val) & 0x3) << 0)
#define LTQ_EBU_CON_0_CMULT_GET(val) ((((val) & LTQ_EBU_CON_0_CMULT) >> 0) & 0x3)
#define LTQ_EBU_CON_0_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_CMULT) | (((val) & 0x3) << 0))
/*******************************************************************************
* External Bus Unit Emulator Bus Configuration Register
******************************************************************************/
/* Write Protection (31) */
#define LTQ_EBU_EMU_BC_WRITE (0x1 << 31)
#define LTQ_EBU_EMU_BC_WRITE_VAL(val) (((val) & 0x1) << 31)
#define LTQ_EBU_EMU_BC_WRITE_GET(val) ((((val) & LTQ_EBU_EMU_BC_WRITE) >> 31) & 0x1)
#define LTQ_EBU_EMU_BC_WRITE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WRITE) | (((val) & 0x1) << 31))
/* Address Generation Control (26:24) */
#define LTQ_EBU_EMU_BC_AGEN (0x7 << 24)
#define LTQ_EBU_EMU_BC_AGEN_VAL(val) (((val) & 0x7) << 24)
#define LTQ_EBU_EMU_BC_AGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_AGEN) >> 24) & 0x7)
#define LTQ_EBU_EMU_BC_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_AGEN) | (((val) & 0x7) << 24))
/* Extended Address Setup Control (22) */
#define LTQ_EBU_EMU_BC_SETUP (0x1 << 22)
#define LTQ_EBU_EMU_BC_SETUP_VAL(val) (((val) & 0x1) << 22)
#define LTQ_EBU_EMU_BC_SETUP_GET(val) ((((val) & LTQ_EBU_EMU_BC_SETUP) >> 22) & 0x1)
#define LTQ_EBU_EMU_BC_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_SETUP) | (((val) & 0x1) << 22))
/* Variable Waitstate Insertion Control (21:20) */
#define LTQ_EBU_EMU_BC_WAIT (0x3 << 20)
#define LTQ_EBU_EMU_BC_WAIT_VAL(val) (((val) & 0x3) << 20)
#define LTQ_EBU_EMU_BC_WAIT_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAIT) >> 20) & 0x3)
#define LTQ_EBU_EMU_BC_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAIT) | (((val) & 0x3) << 20))
/* Active WAIT Level Control (19) */
#define LTQ_EBU_EMU_BC_WINV (0x1 << 19)
#define LTQ_EBU_EMU_BC_WINV_VAL(val) (((val) & 0x1) << 19)
#define LTQ_EBU_EMU_BC_WINV_GET(val) ((((val) & LTQ_EBU_EMU_BC_WINV) >> 19) & 0x1)
#define LTQ_EBU_EMU_BC_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WINV) | (((val) & 0x1) << 19))
/* External Device Data Width Control (17:16) */
#define LTQ_EBU_EMU_BC_PORTW (0x3 << 16)
#define LTQ_EBU_EMU_BC_PORTW_VAL(val) (((val) & 0x3) << 16)
#define LTQ_EBU_EMU_BC_PORTW_GET(val) ((((val) & LTQ_EBU_EMU_BC_PORTW) >> 16) & 0x3)
#define LTQ_EBU_EMU_BC_PORTW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_PORTW) | (((val) & 0x3) << 16))
/* Address Latch Enable Function (15:14) */
#define LTQ_EBU_EMU_BC_ALEC (0x3 << 14)
#define LTQ_EBU_EMU_BC_ALEC_VAL(val) (((val) & 0x3) << 14)
#define LTQ_EBU_EMU_BC_ALEC_GET(val) ((((val) & LTQ_EBU_EMU_BC_ALEC) >> 14) & 0x3)
#define LTQ_EBU_EMU_BC_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_ALEC) | (((val) & 0x3) << 14))
/* Byte Control Signal Timing Mode (13:12) */
#define LTQ_EBU_EMU_BC_BCGEN (0x3 << 12)
#define LTQ_EBU_EMU_BC_BCGEN_VAL(val) (((val) & 0x3) << 12)
#define LTQ_EBU_EMU_BC_BCGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_BCGEN) >> 12) & 0x3)
#define LTQ_EBU_EMU_BC_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_BCGEN) | (((val) & 0x3) << 12))
/* Write Access Waitstate Control (10:8) */
#define LTQ_EBU_EMU_BC_WAITWRC (0x7 << 8)
#define LTQ_EBU_EMU_BC_WAITWRC_VAL(val) (((val) & 0x7) << 8)
#define LTQ_EBU_EMU_BC_WAITWRC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITWRC) >> 8) & 0x7)
#define LTQ_EBU_EMU_BC_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITWRC) | (((val) & 0x7) << 8))
/* Read Access Waitstate Control (7:6) */
#define LTQ_EBU_EMU_BC_WAITRDC (0x3 << 6)
#define LTQ_EBU_EMU_BC_WAITRDC_VAL(val) (((val) & 0x3) << 6)
#define LTQ_EBU_EMU_BC_WAITRDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITRDC) >> 6) & 0x3)
#define LTQ_EBU_EMU_BC_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITRDC) | (((val) & 0x3) << 6))
/* Hold/Pause Cycle Control (5:4) */
#define LTQ_EBU_EMU_BC_HOLDC (0x3 << 4)
#define LTQ_EBU_EMU_BC_HOLDC_VAL(val) (((val) & 0x3) << 4)
#define LTQ_EBU_EMU_BC_HOLDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_HOLDC) >> 4) & 0x3)
#define LTQ_EBU_EMU_BC_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_HOLDC) | (((val) & 0x3) << 4))
/* Recovery Cycles Control (3:2) */
#define LTQ_EBU_EMU_BC_RECOVC (0x3 << 2)
#define LTQ_EBU_EMU_BC_RECOVC_VAL(val) (((val) & 0x3) << 2)
#define LTQ_EBU_EMU_BC_RECOVC_GET(val) ((((val) & LTQ_EBU_EMU_BC_RECOVC) >> 2) & 0x3)
#define LTQ_EBU_EMU_BC_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_RECOVC) | (((val) & 0x3) << 2))
/* Cycle Multiplier Control (1:0) */
#define LTQ_EBU_EMU_BC_CMULT (0x3)
#define LTQ_EBU_EMU_BC_CMULT_VAL(val) (((val) & 0x3) << 0)
#define LTQ_EBU_EMU_BC_CMULT_GET(val) ((((val) & LTQ_EBU_EMU_BC_CMULT) >> 0) & 0x3)
#define LTQ_EBU_EMU_BC_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_CMULT) | (((val) & 0x3) << 0))
/*******************************************************************************
* PC-Card Control Register
******************************************************************************/
/* External Interrupt Input IREQ (3:1) */
#define LTQ_EBU_PCC_CON_IREQ (0x7 << 1)
#define LTQ_EBU_PCC_CON_IREQ_VAL(val) (((val) & 0x7) << 1)
#define LTQ_EBU_PCC_CON_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_CON_IREQ) >> 1) & 0x7)
#define LTQ_EBU_PCC_CON_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_IREQ) | (((val) & 0x7) << 1))
/* PC Card ON (0) */
#define LTQ_EBU_PCC_CON_ON (0x1)
#define LTQ_EBU_PCC_CON_ON_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_PCC_CON_ON_GET(val) ((((val) & LTQ_EBU_PCC_CON_ON) >> 0) & 0x1)
#define LTQ_EBU_PCC_CON_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_ON) | (((val) & 0x1) << 0))
/*******************************************************************************
* PCC Status Register
******************************************************************************/
/* Interrupt Request (6) */
#define LTQ_EBU_PCC_STAT_IRQ (0x1 << 6)
#define LTQ_EBU_PCC_STAT_IRQ_GET(val) ((((val) & LTQ_EBU_PCC_STAT_IRQ) >> 6) & 0x1)
/* PC-Card Overcurrent (5) */
#define LTQ_EBU_PCC_STAT_OC (0x1 << 5)
#define LTQ_EBU_PCC_STAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_STAT_OC) >> 5) & 0x1)
/* PC-Card Socket Power On (4) */
#define LTQ_EBU_PCC_STAT_SPON (0x1 << 4)
#define LTQ_EBU_PCC_STAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_STAT_SPON) >> 4) & 0x1)
/* Card Detect Status (1:0) */
#define LTQ_EBU_PCC_STAT_CD (0x3)
#define LTQ_EBU_PCC_STAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_STAT_CD) >> 0) & 0x3)
/*******************************************************************************
* PCC Interrupt Status Register
******************************************************************************/
/* Interrupt Request Active Interrupt (4) */
#define LTQ_EBU_PCC_ISTAT_IREQ (0x1 << 4)
#define LTQ_EBU_PCC_ISTAT_IREQ_VAL(val) (((val) & 0x1) << 4)
#define LTQ_EBU_PCC_ISTAT_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_IREQ) >> 4) & 0x1)
#define LTQ_EBU_PCC_ISTAT_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_IREQ) | (((val) & 0x1) << 4))
/* Over Current Status Change Interrupt (3) */
#define LTQ_EBU_PCC_ISTAT_OC (0x1 << 3)
#define LTQ_EBU_PCC_ISTAT_OC_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_PCC_ISTAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_OC) >> 3) & 0x1)
#define LTQ_EBU_PCC_ISTAT_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_OC) | (((val) & 0x1) << 3))
/* Socket Power on Status Change Interrupt (2) */
#define LTQ_EBU_PCC_ISTAT_SPON (0x1 << 2)
#define LTQ_EBU_PCC_ISTAT_SPON_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_PCC_ISTAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_SPON) >> 2) & 0x1)
#define LTQ_EBU_PCC_ISTAT_SPON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_SPON) | (((val) & 0x1) << 2))
/* Voltage Sense Status Change Interrupt (1) */
#define LTQ_EBU_PCC_ISTAT_VS (0x1 << 1)
#define LTQ_EBU_PCC_ISTAT_VS_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_PCC_ISTAT_VS_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_VS) >> 1) & 0x1)
#define LTQ_EBU_PCC_ISTAT_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_VS) | (((val) & 0x1) << 1))
/* Card Detect Status Change Interrupt (0) */
#define LTQ_EBU_PCC_ISTAT_CD (0x1)
#define LTQ_EBU_PCC_ISTAT_CD_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_PCC_ISTAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_CD) >> 0) & 0x1)
#define LTQ_EBU_PCC_ISTAT_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_CD) | (((val) & 0x1) << 0))
/*******************************************************************************
* PCC Interrupt Enable Register
******************************************************************************/
/* Enable of Interrupt Request IR (4) */
#define LTQ_EBU_PCC_IEN_IR (0x1 << 4)
#define LTQ_EBU_PCC_IEN_IR_VAL(val) (((val) & 0x1) << 4)
#define LTQ_EBU_PCC_IEN_IR_GET(val) ((((val) & LTQ_EBU_PCC_IEN_IR) >> 4) & 0x1)
#define LTQ_EBU_PCC_IEN_IR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_IR) | (((val) & 0x1) << 4))
/* Enable of Interrupt Request OC event (3) */
#define LTQ_EBU_PCC_IEN_OC (0x1 << 3)
#define LTQ_EBU_PCC_IEN_OC_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_PCC_IEN_OC_GET(val) ((((val) & LTQ_EBU_PCC_IEN_OC) >> 3) & 0x1)
#define LTQ_EBU_PCC_IEN_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_OC) | (((val) & 0x1) << 3))
/* Enable of Interrupt Request Socket Power On (2) */
#define LTQ_EBU_PCC_IEN_PWRON (0x1 << 2)
#define LTQ_EBU_PCC_IEN_PWRON_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_PCC_IEN_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_IEN_PWRON) >> 2) & 0x1)
#define LTQ_EBU_PCC_IEN_PWRON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_PWRON) | (((val) & 0x1) << 2))
/* Enable of Interrupt Request Voltage Sense (1) */
#define LTQ_EBU_PCC_IEN_VS (0x1 << 1)
#define LTQ_EBU_PCC_IEN_VS_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_PCC_IEN_VS_GET(val) ((((val) & LTQ_EBU_PCC_IEN_VS) >> 1) & 0x1)
#define LTQ_EBU_PCC_IEN_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_VS) | (((val) & 0x1) << 1))
/* Enable of Interrupt Request Card Detect (0) */
#define LTQ_EBU_PCC_IEN_CD (0x1)
#define LTQ_EBU_PCC_IEN_CD_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_PCC_IEN_CD_GET(val) ((((val) & LTQ_EBU_PCC_IEN_CD) >> 0) & 0x1)
#define LTQ_EBU_PCC_IEN_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_CD) | (((val) & 0x1) << 0))
/*******************************************************************************
* PCC Interrupt Output Status Register
******************************************************************************/
/* Status of Interrupt Request IR (4) */
#define LTQ_EBU_PCC_INT_OUT_IR (0x1 << 4)
#define LTQ_EBU_PCC_INT_OUT_IR_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_IR) >> 4) & 0x1)
/* Status of Interrupt Request OC (3) */
#define LTQ_EBU_PCC_INT_OUT_OC (0x1 << 3)
#define LTQ_EBU_PCC_INT_OUT_OC_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_OC) >> 3) & 0x1)
/* Status of Interrupt Request Socket Power On (2) */
#define LTQ_EBU_PCC_INT_OUT_PWRON (0x1 << 2)
#define LTQ_EBU_PCC_INT_OUT_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_PWRON) >> 2) & 0x1)
/* Status of Interrupt Request Voltage Sense (1) */
#define LTQ_EBU_PCC_INT_OUT_VS (0x1 << 1)
#define LTQ_EBU_PCC_INT_OUT_VS_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_VS) >> 1) & 0x1)
/* Status of Interrupt Request Card Detect (0) */
#define LTQ_EBU_PCC_INT_OUT_CD (0x1)
#define LTQ_EBU_PCC_INT_OUT_CD_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_CD) >> 0) & 0x1)
/*******************************************************************************
* PCC Interrupt Request Set Register
******************************************************************************/
/* Set Interrupt Request IR (4) */
#define LTQ_EBU_PCC_IRS_IR (0x1 << 4)
#define LTQ_EBU_PCC_IRS_IR_VAL(val) (((val) & 0x1) << 4)
#define LTQ_EBU_PCC_IRS_IR_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_IR) | (val) & 1) << 4)
/* Set Interrupt Request OC (3) */
#define LTQ_EBU_PCC_IRS_OC (0x1 << 3)
#define LTQ_EBU_PCC_IRS_OC_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_PCC_IRS_OC_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_OC) | (val) & 1) << 3)
/* Set Interrupt Request Socket Power On (2) */
#define LTQ_EBU_PCC_IRS_PWRON (0x1 << 2)
#define LTQ_EBU_PCC_IRS_PWRON_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_PCC_IRS_PWRON_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_PWRON) | (val) & 1) << 2)
/* Set Interrupt Request Voltage Sense (1) */
#define LTQ_EBU_PCC_IRS_VS (0x1 << 1)
#define LTQ_EBU_PCC_IRS_VS_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_PCC_IRS_VS_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_VS) | (val) & 1) << 1)
/* Set Interrupt Request Card Detect (0) */
#define LTQ_EBU_PCC_IRS_CD (0x1)
#define LTQ_EBU_PCC_IRS_CD_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_PCC_IRS_CD_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_CD) | (val) & 1) << 0)
/*******************************************************************************
* NAND Flash Control Register
******************************************************************************/
/* ECC Enabling (31) */
#define LTQ_EBU_NAND_CON_ECC_ON (0x1 << 31)
#define LTQ_EBU_NAND_CON_ECC_ON_VAL(val) (((val) & 0x1) << 31)
#define LTQ_EBU_NAND_CON_ECC_ON_GET(val) ((((val) & LTQ_EBU_NAND_CON_ECC_ON) >> 31) & 0x1)
#define LTQ_EBU_NAND_CON_ECC_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ECC_ON) | (((val) & 0x1) << 31))
/* Latch enable (23:18) */
#define LTQ_EBU_NAND_CON_LAT_EN (0x3f << 18)
#define LTQ_EBU_NAND_CON_LAT_EN_VAL(val) (((val) & 0x3f) << 18)
#define LTQ_EBU_NAND_CON_LAT_EN_GET(val) ((((val) & LTQ_EBU_NAND_CON_LAT_EN) >> 18) & 0x3f)
#define LTQ_EBU_NAND_CON_LAT_EN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_LAT_EN) | (((val) & 0x3f) << 18))
/* Output ChipSelect# Selection (11:10) */
#define LTQ_EBU_NAND_CON_OUT_CS_S (0x3 << 10)
#define LTQ_EBU_NAND_CON_OUT_CS_S_VAL(val) (((val) & 0x3) << 10)
#define LTQ_EBU_NAND_CON_OUT_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_OUT_CS_S) >> 10) & 0x3)
#define LTQ_EBU_NAND_CON_OUT_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_OUT_CS_S) | (((val) & 0x3) << 10))
/* Input ChipSelect# Selection (9:8) */
#define LTQ_EBU_NAND_CON_IN_CS_S (0x3 << 8)
#define LTQ_EBU_NAND_CON_IN_CS_S_VAL(val) (((val) & 0x3) << 8)
#define LTQ_EBU_NAND_CON_IN_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_IN_CS_S) >> 8) & 0x3)
#define LTQ_EBU_NAND_CON_IN_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_IN_CS_S) | (((val) & 0x3) << 8))
/* Set PRE (7) */
#define LTQ_EBU_NAND_CON_PRE_P (0x1 << 7)
#define LTQ_EBU_NAND_CON_PRE_P_VAL(val) (((val) & 0x1) << 7)
#define LTQ_EBU_NAND_CON_PRE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_PRE_P) >> 7) & 0x1)
#define LTQ_EBU_NAND_CON_PRE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_PRE_P) | (((val) & 0x1) << 7))
/* Set WP Active Polarity (6) */
#define LTQ_EBU_NAND_CON_WP_P (0x1 << 6)
#define LTQ_EBU_NAND_CON_WP_P_VAL(val) (((val) & 0x1) << 6)
#define LTQ_EBU_NAND_CON_WP_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_WP_P) >> 6) & 0x1)
#define LTQ_EBU_NAND_CON_WP_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_WP_P) | (((val) & 0x1) << 6))
/* Set SE Active Polarity (5) */
#define LTQ_EBU_NAND_CON_SE_P (0x1 << 5)
#define LTQ_EBU_NAND_CON_SE_P_VAL(val) (((val) & 0x1) << 5)
#define LTQ_EBU_NAND_CON_SE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_SE_P) >> 5) & 0x1)
#define LTQ_EBU_NAND_CON_SE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_SE_P) | (((val) & 0x1) << 5))
/* Set CS Active Polarity (4) */
#define LTQ_EBU_NAND_CON_CS_P (0x1 << 4)
#define LTQ_EBU_NAND_CON_CS_P_VAL(val) (((val) & 0x1) << 4)
#define LTQ_EBU_NAND_CON_CS_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CS_P) >> 4) & 0x1)
#define LTQ_EBU_NAND_CON_CS_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CS_P) | (((val) & 0x1) << 4))
/* Set CLE Active Polarity (3) */
#define LTQ_EBU_NAND_CON_CLE_P (0x1 << 3)
#define LTQ_EBU_NAND_CON_CLE_P_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_NAND_CON_CLE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CLE_P) >> 3) & 0x1)
#define LTQ_EBU_NAND_CON_CLE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CLE_P) | (((val) & 0x1) << 3))
/* Set ALE Active Polarity (2) */
#define LTQ_EBU_NAND_CON_ALE_P (0x1 << 2)
#define LTQ_EBU_NAND_CON_ALE_P_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_NAND_CON_ALE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_ALE_P) >> 2) & 0x1)
#define LTQ_EBU_NAND_CON_ALE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ALE_P) | (((val) & 0x1) << 2))
/* NAND CS Mux with EBU CS Enable (1) */
#define LTQ_EBU_NAND_CON_CSMUX_E (0x1 << 1)
#define LTQ_EBU_NAND_CON_CSMUX_E_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_NAND_CON_CSMUX_E_GET(val) ((((val) & LTQ_EBU_NAND_CON_CSMUX_E) >> 1) & 0x1)
#define LTQ_EBU_NAND_CON_CSMUX_E_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CSMUX_E) | (((val) & 0x1) << 1))
/* NAND FLASH Mode Support (0) */
#define LTQ_EBU_NAND_CON_NANDMODE (0x1)
#define LTQ_EBU_NAND_CON_NANDMODE_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_NAND_CON_NANDMODE_GET(val) ((((val) & LTQ_EBU_NAND_CON_NANDMODE) >> 0) & 0x1)
#define LTQ_EBU_NAND_CON_NANDMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_NANDMODE) | (((val) & 0x1) << 0))
/*******************************************************************************
* NAND Flash State Register
******************************************************************************/
/* Reserved (31:3) */
#define LTQ_EBU_NAND_WAIT_RES (0x1fffffff << 3)
#define LTQ_EBU_NAND_WAIT_RES_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RES) >> 3) & 0x1fffffff)
/* NAND Write Complete (3) */
#define LTQ_EBU_NAND_WAIT_WR_C (0x1 << 3)
#define LTQ_EBU_NAND_WAIT_WR_C_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_WR_C) >> 3) & 0x1)
/* Record the RD Edge (rising ) (2) */
#define LTQ_EBU_NAND_WAIT_RD_EDGE (0x1 << 2)
#define LTQ_EBU_NAND_WAIT_RD_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RD_EDGE) >> 2) & 0x1)
/* Record the BY# Edge (falling) (1) */
#define LTQ_EBU_NAND_WAIT_BY_EDGE (0x1 << 1)
#define LTQ_EBU_NAND_WAIT_BY_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_BY_EDGE) >> 1) & 0x1)
/* Rd/BY# value (0) */
#define LTQ_EBU_NAND_WAIT_RDBY_VALUE (0x1)
#define LTQ_EBU_NAND_WAIT_RDBY_VALUE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RDBY_VALUE) >> 0) & 0x1)
/*******************************************************************************
* NAND ECC Result Register 0
******************************************************************************/
/* Reserved (31:24) */
#define LTQ_EBU_NAND_ECC0_RES (0xff << 24)
#define LTQ_EBU_NAND_ECC0_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_RES) >> 24) & 0xff)
/* ECC value (23:16) */
#define LTQ_EBU_NAND_ECC0_ECC_B2 (0xff << 16)
#define LTQ_EBU_NAND_ECC0_ECC_B2_VAL(val) (((val) & 0xff) << 16)
#define LTQ_EBU_NAND_ECC0_ECC_B2_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B2) >> 16) & 0xff)
#define LTQ_EBU_NAND_ECC0_ECC_B2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B2) | (((val) & 0xff) << 16))
/* ECC value (15:8) */
#define LTQ_EBU_NAND_ECC0_ECC_B1 (0xff << 8)
#define LTQ_EBU_NAND_ECC0_ECC_B1_VAL(val) (((val) & 0xff) << 8)
#define LTQ_EBU_NAND_ECC0_ECC_B1_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B1) >> 8) & 0xff)
#define LTQ_EBU_NAND_ECC0_ECC_B1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B1) | (((val) & 0xff) << 8))
/* ECC value (7:0) */
#define LTQ_EBU_NAND_ECC0_ECC_B0 (0xff)
#define LTQ_EBU_NAND_ECC0_ECC_B0_VAL(val) (((val) & 0xff) << 0)
#define LTQ_EBU_NAND_ECC0_ECC_B0_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B0) >> 0) & 0xff)
#define LTQ_EBU_NAND_ECC0_ECC_B0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B0) | (((val) & 0xff) << 0))
/*******************************************************************************
* NAND ECC Address Counter Register
******************************************************************************/
/* Reserved (31:9) */
#define LTQ_EBU_NAND_ECC_AC_RES (0x7fffff << 9)
#define LTQ_EBU_NAND_ECC_AC_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_RES) >> 9) & 0x7fffff)
/* ECC address counter (8:0) */
#define LTQ_EBU_NAND_ECC_AC_ECC_AC (0x1ff)
#define LTQ_EBU_NAND_ECC_AC_ECC_AC_VAL(val) (((val) & 0x1ff) << 0)
#define LTQ_EBU_NAND_ECC_AC_ECC_AC_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_ECC_AC) >> 0) & 0x1ff)
#define LTQ_EBU_NAND_ECC_AC_ECC_AC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC_AC_ECC_AC) | (((val) & 0x1ff) << 0))
/*******************************************************************************
* Internal Address Emulation Register
******************************************************************************/
/* Memory Region Base Address (31:12) */
#define LTQ_EBU_EMU_ADDR_BASE (0xfffff << 12)
#define LTQ_EBU_EMU_ADDR_BASE_VAL(val) (((val) & 0xfffff) << 12)
#define LTQ_EBU_EMU_ADDR_BASE_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_BASE) >> 12) & 0xfffff)
#define LTQ_EBU_EMU_ADDR_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_BASE) | (((val) & 0xfffff) << 12))
/* Memory Region Address Mask (7:4) */
#define LTQ_EBU_EMU_ADDR_MASK (0xf << 4)
#define LTQ_EBU_EMU_ADDR_MASK_VAL(val) (((val) & 0xf) << 4)
#define LTQ_EBU_EMU_ADDR_MASK_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MASK) >> 4) & 0xf)
#define LTQ_EBU_EMU_ADDR_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MASK) | (((val) & 0xf) << 4))
/* Memory Region Mirror Segment B Control (1) */
#define LTQ_EBU_EMU_ADDR_MRMB (0x1 << 1)
#define LTQ_EBU_EMU_ADDR_MRMB_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_EMU_ADDR_MRMB_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MRMB) >> 1) & 0x1)
#define LTQ_EBU_EMU_ADDR_MRMB_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MRMB) | (((val) & 0x1) << 1))
/* Memory Region Enable Control (0) */
#define LTQ_EBU_EMU_ADDR_MREC (0x1)
#define LTQ_EBU_EMU_ADDR_MREC_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_EMU_ADDR_MREC_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MREC) >> 0) & 0x1)
#define LTQ_EBU_EMU_ADDR_MREC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MREC) | (((val) & 0x1) << 0))
/*******************************************************************************
* nternal Emulator Configuration Register
******************************************************************************/
/* Overlay Memory Control Region 3 (3) */
#define LTQ_EBU_EMU_CON_OVL3 (0x1 << 3)
#define LTQ_EBU_EMU_CON_OVL3_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_EMU_CON_OVL3_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL3) >> 3) & 0x1)
#define LTQ_EBU_EMU_CON_OVL3_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL3) | (((val) & 0x1) << 3))
/* Overlay Memory Control Region 2 (2) */
#define LTQ_EBU_EMU_CON_OVL2 (0x1 << 2)
#define LTQ_EBU_EMU_CON_OVL2_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_EMU_CON_OVL2_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL2) >> 2) & 0x1)
#define LTQ_EBU_EMU_CON_OVL2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL2) | (((val) & 0x1) << 2))
/* Overlay Memory Control Region 1 (1) */
#define LTQ_EBU_EMU_CON_OVL1 (0x1 << 1)
#define LTQ_EBU_EMU_CON_OVL1_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_EMU_CON_OVL1_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL1) >> 1) & 0x1)
#define LTQ_EBU_EMU_CON_OVL1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL1) | (((val) & 0x1) << 1))
/* Overlay Memory Control Region 0 (0) */
#define LTQ_EBU_EMU_CON_OVL0 (0x1)
#define LTQ_EBU_EMU_CON_OVL0_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_EMU_CON_OVL0_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL0) >> 0) & 0x1)
#define LTQ_EBU_EMU_CON_OVL0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL0) | (((val) & 0x1) << 0))
#endif /* __LTQ_EBU_H */

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/*
* arch/mips/include/asm/mach-lantiq/svip/irq.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2010 Lantiq
*
*/
#ifndef __IRQ_H
#define __IRQ_H
#include <svip_irq.h>
#define NR_IRQS 264
#include_next <irq.h>
/* Functions for EXINT handling */
extern int ifx_enable_external_int(u32 exint, u32 mode);
extern int ifx_disable_external_int(u32 exint);
extern int ifx_external_int_level(u32 exint);
#endif

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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#ifndef _LTQ_SVIP_H__
#define _LTQ_SVIP_H__
#ifdef CONFIG_SOC_SVIP
#include <lantiq.h>
/* Chip IDs */
#define SOC_ID_SVIP 0x169
/* SoC Types */
#define SOC_TYPE_SVIP 0x01
/* ASC0/1 - serial port */
#define LTQ_ASC0_BASE_ADDR 0x14100100
#define LTQ_ASC1_BASE_ADDR 0x14100200
#define LTQ_ASC_SIZE 0x100
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
#define LTQ_ASC_TIR(x) (INT_NUM_IM0_IRL0 + (x * 8))
#define LTQ_ASC_RIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 2)
#define LTQ_ASC_EIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 3)
/* ICU - interrupt control unit */
#define LTQ_ICU_BASE_ADDR 0x14106000
#define LTQ_ICU_BASE_ADDR1 0x14106028
#define LTQ_ICU_BASE_ADDR2 0x1E016000
#define LTQ_ICU_BASE_ADDR3 0x1E016028
#define LTQ_ICU_BASE_ADDR4 0x14106050
#define LTQ_ICU_BASE_ADDR5 0x14106078
#define LTQ_ICU_SIZE 0x100
/* WDT */
#define LTQ_WDT_BASE_ADDR 0x1F8803F0
#define LTQ_WDT_SIZE 0x10
/* Status */
#define LTQ_STATUS_BASE_ADDR (KSEG1 + 0x1E000500)
#define LTQ_STATUS_CHIPID ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C))
#define LTQ_EIU_BASE_ADDR 0
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
extern __iomem void *ltq_ebu_membase;
extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen,
bool altsel0, bool altsel1);
extern int ltq_port_get_dir(unsigned int port, unsigned int pin);
extern int ltq_port_get_puden(unsigned int port, unsigned int pin);
extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin);
extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin);
#define ltq_is_ar9() 0
#define ltq_is_vr9() 0
#define ltq_is_falcon() 0
#define BS_FLASH 0
#define LTQ_RST_CAUSE_WDTRST 0x2
#endif /* CONFIG_SOC_SVIP */
#endif /* _LTQ_SVIP_H__ */

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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __MPS_REG_H
#define __MPS_REG_H
#define mbs_r32(reg) ltq_r32(&mbs->reg)
#define mbs_w32(val, reg) ltq_w32(val, &mbs->reg)
#define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg)
/** MBS register structure */
struct svip_reg_mbs {
unsigned long reserved0[4];
unsigned long mbsr0; /* 0x0010 */
unsigned long mbsr1; /* 0x0014 */
unsigned long mbsr2; /* 0x0018 */
unsigned long mbsr3; /* 0x001c */
unsigned long mbsr4; /* 0x0020 */
unsigned long mbsr5; /* 0x0024 */
unsigned long mbsr6; /* 0x0028 */
unsigned long mbsr7; /* 0x002c */
unsigned long mbsr8; /* 0x0030 */
unsigned long mbsr9; /* 0x0034 */
unsigned long mbsr10; /* 0x0038 */
unsigned long mbsr11; /* 0x003c */
unsigned long mbsr12; /* 0x0040 */
unsigned long mbsr13; /* 0x0044 */
unsigned long mbsr14; /* 0x0048 */
unsigned long mbsr15; /* 0x004c */
unsigned long mbsr16; /* 0x0050 */
unsigned long mbsr17; /* 0x0054 */
unsigned long mbsr18; /* 0x0058 */
unsigned long mbsr19; /* 0x005c */
unsigned long mbsr20; /* 0x0060 */
unsigned long mbsr21; /* 0x0064 */
unsigned long mbsr22; /* 0x0068 */
unsigned long mbsr23; /* 0x006c */
unsigned long mbsr24; /* 0x0070 */
unsigned long mbsr25; /* 0x0074 */
unsigned long mbsr26; /* 0x0078 */
unsigned long mbsr27; /* 0x007c */
unsigned long mbsr28; /* 0x0080 */
};
/** MPS register structure */
struct svip_reg_mps {
volatile unsigned long mps_swirn0set; /* 0x0000 */
volatile unsigned long mps_swirn0en; /* 0x0004 */
volatile unsigned long mps_swirn0cr; /* 0x0008 */
volatile unsigned long mps_swirn0icr; /* 0x000C */
volatile unsigned long mps_swirn1set; /* 0x0010 */
volatile unsigned long mps_swirn1en; /* 0x0014 */
volatile unsigned long mps_swirn1cr; /* 0x0018 */
volatile unsigned long mps_swirn1icr; /* 0x001C */
volatile unsigned long mps_swirn2set; /* 0x0020 */
volatile unsigned long mps_swirn2en; /* 0x0024 */
volatile unsigned long mps_swirn2cr; /* 0x0028 */
volatile unsigned long mps_swirn2icr; /* 0x002C */
volatile unsigned long mps_swirn3set; /* 0x0030 */
volatile unsigned long mps_swirn3en; /* 0x0034 */
volatile unsigned long mps_swirn3cr; /* 0x0038 */
volatile unsigned long mps_swirn3icr; /* 0x003C */
volatile unsigned long mps_swirn4set; /* 0x0040 */
volatile unsigned long mps_swirn4en; /* 0x0044 */
volatile unsigned long mps_swirn4cr; /* 0x0048 */
volatile unsigned long mps_swirn4icr; /* 0x004C */
volatile unsigned long mps_swirn5set; /* 0x0050 */
volatile unsigned long mps_swirn5en; /* 0x0054 */
volatile unsigned long mps_swirn5cr; /* 0x0058 */
volatile unsigned long mps_swirn5icr; /* 0x005C */
volatile unsigned long mps_swirn6set; /* 0x0060 */
volatile unsigned long mps_swirn6en; /* 0x0064 */
volatile unsigned long mps_swirn6cr; /* 0x0068 */
volatile unsigned long mps_swirn6icr; /* 0x006C */
volatile unsigned long mps_swirn7set; /* 0x0070 */
volatile unsigned long mps_swirn7en; /* 0x0074 */
volatile unsigned long mps_swirn7cr; /* 0x0078 */
volatile unsigned long mps_swirn7icr; /* 0x007C */
volatile unsigned long mps_swirn8set; /* 0x0080 */
volatile unsigned long mps_swirn8en; /* 0x0084 */
volatile unsigned long mps_swirn8cr; /* 0x0088 */
volatile unsigned long mps_swirn8icr; /* 0x008C */
};
/* Software Interrupt */
#define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000))
#define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004))
#define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008))
#define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C))
#define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010))
#define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014))
#define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018))
#define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C))
#define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020))
#define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024))
#define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028))
#define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C))
#define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030))
#define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034))
#define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038))
#define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C))
#define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040))
#define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044))
#define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048))
#define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C))
#define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050))
#define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054))
#define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058))
#define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C))
#define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060))
#define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064))
#define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068))
#define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C))
#define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070))
#define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074))
#define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078))
#define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C))
#define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080))
#define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084))
#define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C))
#define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088))
/*******************************************************************************
* MPS_SWIRNSET Register
******************************************************************************/
/* Software Interrupt Request IR5 (5) */
#define IFX_MPS_SWIRNSET_IR5 (0x1 << 5)
#define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5)
#define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5)
/* Software Interrupt Request IR4 (4) */
#define IFX_MPS_SWIRNSET_IR4 (0x1 << 4)
#define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4)
#define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4)
/* Software Interrupt Request IR3 (3) */
#define IFX_MPS_SWIRNSET_IR3 (0x1 << 3)
#define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3)
#define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3)
/* Software Interrupt Request IR2 (2) */
#define IFX_MPS_SWIRNSET_IR2 (0x1 << 2)
#define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2)
#define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2)
/* Software Interrupt Request IR1 (1) */
#define IFX_MPS_SWIRNSET_IR1 (0x1 << 1)
#define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1)
#define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1)
/* Software Interrupt Request IR0 (0) */
#define IFX_MPS_SWIRNSET_IR0 (0x1)
#define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0)
#define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0)
/*******************************************************************************
* MPS_SWIRNEN Register
******************************************************************************/
/* Software Interrupt Request IR5 (5) */
#define IFX_MPS_SWIRNEN_IR5 (0x1 << 5)
#define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5)
#define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1)
#define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5))
/* Software Interrupt Request IR4 (4) */
#define IFX_MPS_SWIRNEN_IR4 (0x1 << 4)
#define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4)
#define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1)
#define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4))
/* Software Interrupt Request IR3 (3) */
#define IFX_MPS_SWIRNEN_IR3 (0x1 << 3)
#define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3)
#define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1)
#define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3))
/* Software Interrupt Request IR2 (2) */
#define IFX_MPS_SWIRNEN_IR2 (0x1 << 2)
#define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2)
#define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1)
#define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2))
/* Software Interrupt Request IR1 (1) */
#define IFX_MPS_SWIRNEN_IR1 (0x1 << 1)
#define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1)
#define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1)
#define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1))
/* Software Interrupt Request IR0 (0) */
#define IFX_MPS_SWIRNEN_IR0 (0x1)
#define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0)
#define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1)
#define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0))
/*******************************************************************************
* MPS_SWIRNICR Register
******************************************************************************/
/* Software Interrupt Request IR5 (5) */
#define IFX_MPS_SWIRNICR_IR5 (0x1 << 5)
#define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1)
/* Software Interrupt Request IR4 (4) */
#define IFX_MPS_SWIRNICR_IR4 (0x1 << 4)
#define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1)
/* Software Interrupt Request IR3 (3) */
#define IFX_MPS_SWIRNICR_IR3 (0x1 << 3)
#define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1)
/* Software Interrupt Request IR2 (2) */
#define IFX_MPS_SWIRNICR_IR2 (0x1 << 2)
#define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1)
/* Software Interrupt Request IR1 (1) */
#define IFX_MPS_SWIRNICR_IR1 (0x1 << 1)
#define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1)
/* Software Interrupt Request IR0 (0) */
#define IFX_MPS_SWIRNICR_IR0 (0x1)
#define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1)
/*******************************************************************************
* MPS_SWIRNCR Register
******************************************************************************/
/* Software Interrupt Request IR5 (5) */
#define IFX_MPS_SWIRNCR_IR5 (0x1 << 5)
#define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1)
/* Software Interrupt Request IR4 (4) */
#define IFX_MPS_SWIRNCR_IR4 (0x1 << 4)
#define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1)
/* Software Interrupt Request IR3 (3) */
#define IFX_MPS_SWIRNCR_IR3 (0x1 << 3)
#define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1)
/* Software Interrupt Request IR2 (2) */
#define IFX_MPS_SWIRNCR_IR2 (0x1 << 2)
#define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1)
/* Software Interrupt Request IR1 (1) */
#define IFX_MPS_SWIRNCR_IR1 (0x1 << 1)
#define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1)
/* Software Interrupt Request IR0 (0) */
#define IFX_MPS_SWIRNCR_IR0 (0x1)
#define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1)
#endif

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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __SSC_REG_H
#define __SSC_REG_H
/** SSC register structure */
struct svip_reg_ssc {
volatile unsigned long clc; /* 0x00 */
volatile unsigned long pisel; /* 0x04 */
volatile unsigned long id; /* 0x08 */
volatile unsigned long reserved0; /* 0x0c */
volatile unsigned long mcon; /* 0x10 */
volatile unsigned long state; /* 0x14 */
volatile unsigned long whbstate; /* 0x18 */
volatile unsigned long reserved1; /* 0x1c */
volatile unsigned long tb; /* 0x20 */
volatile unsigned long rb; /* 0x24 */
volatile unsigned long reserved2[2]; /* 0x28 */
volatile unsigned long rxfcon; /* 0x30 */
volatile unsigned long txfcon; /* 0x34 */
volatile unsigned long fstat; /* 0x38 */
volatile unsigned long reserved3; /* 0x3c */
volatile unsigned long br; /* 0x40 */
volatile unsigned long brstat; /* 0x44 */
volatile unsigned long reserved4[6]; /* 0x48 */
volatile unsigned long sfcon; /* 0x60 */
volatile unsigned long sfstat; /* 0x64 */
volatile unsigned long reserved5[2]; /* 0x68 */
volatile unsigned long gpocon; /* 0x70 */
volatile unsigned long gpostat; /* 0x74 */
volatile unsigned long whbgpostat; /* 0x78 */
volatile unsigned long reserved6; /* 0x7c */
volatile unsigned long rxreq; /* 0x80 */
volatile unsigned long rxcnt; /* 0x84 */
volatile unsigned long reserved7[25]; /* 0x88 */
volatile unsigned long dma_con; /* 0xEC */
volatile unsigned long reserved8; /* 0xf0 */
volatile unsigned long irnen; /* 0xF4 */
volatile unsigned long irncr; /* 0xF8 */
volatile unsigned long irnicr; /* 0xFC */
};
/*******************************************************************************
* CLC Register
******************************************************************************/
/* Clock Divider for Sleep Mode (23:16) */
#define SSC_CLC_SMC (0xff << 16)
#define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16)
#define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff)
#define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16))
/* Clock Divider for Normal Run Mode (15:8) */
#define SSC_CLC_RMC (0xff << 8)
#define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8)
#define SSC_CLC_RMC_GET(val) ((((val) & SSC_CLC_RMC) >> 8) & 0xff)
#define SSC_CLC_RMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_RMC) | (((val) & 0xff) << 8))
/* Fast Shut-Off Enable Bit (5) */
#define SSC_CLC_FSOE (0x1 << 5)
#define SSC_CLC_FSOE_VAL(val) (((val) & 0x1) << 5)
#define SSC_CLC_FSOE_GET(val) ((((val) & SSC_CLC_FSOE) >> 5) & 0x1)
#define SSC_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~SSC_CLC_FSOE) | (((val) & 0x1) << 5))
/* Suspend Bit Write Enable for OCDS (4) */
#define SSC_CLC_SBWE (0x1 << 4)
#define SSC_CLC_SBWE_VAL(val) (((val) & 0x1) << 4)
#define SSC_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~SSC_CLC_SBWE) | (val) & 1) << 4)
/* External Request Disable (3) */
#define SSC_CLC_EDIS (0x1 << 3)
#define SSC_CLC_EDIS_VAL(val) (((val) & 0x1) << 3)
#define SSC_CLC_EDIS_GET(val) ((((val) & SSC_CLC_EDIS) >> 3) & 0x1)
#define SSC_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~SSC_CLC_EDIS) | (((val) & 0x1) << 3))
/* Suspend Enable Bit for OCDS (2) */
#define SSC_CLC_SPEN (0x1 << 2)
#define SSC_CLC_SPEN_VAL(val) (((val) & 0x1) << 2)
#define SSC_CLC_SPEN_GET(val) ((((val) & SSC_CLC_SPEN) >> 2) & 0x1)
#define SSC_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SPEN) | (((val) & 0x1) << 2))
/* Disable Status Bit (1) */
#define SSC_CLC_DISS (0x1 << 1)
#define SSC_CLC_DISS_GET(val) ((((val) & SSC_CLC_DISS) >> 1) & 0x1)
/* Disable Request Bit (0) */
#define SSC_CLC_DISR (0x1)
#define SSC_CLC_DISR_VAL(val) (((val) & 0x1) << 0)
#define SSC_CLC_DISR_GET(val) ((((val) & SSC_CLC_DISR) >> 0) & 0x1)
#define SSC_CLC_DISR_SET(reg,val) (reg) = ((reg & ~SSC_CLC_DISR) | (((val) & 0x1) << 0))
/*******************************************************************************
* ID Register
******************************************************************************/
/* Transmit FIFO Size (29:24) */
#define SSC_ID_TXFS (0x3f << 24)
#define SSC_ID_TXFS_GET(val) ((((val) & SSC_ID_TXFS) >> 24) & 0x3f)
/* Receive FIFO Size (21:16) */
#define SSC_ID_RXFS (0x3f << 16)
#define SSC_ID_RXFS_GET(val) ((((val) & SSC_ID_RXFS) >> 16) & 0x3f)
/* Module ID (15:8) */
#define SSC_ID_ID (0xff << 8)
#define SSC_ID_ID_GET(val) ((((val) & SSC_ID_ID) >> 8) & 0xff)
/* Configuration (5) */
#define SSC_ID_CFG (0x1 << 5)
#define SSC_ID_CFG_GET(val) ((((val) & SSC_ID_CFG) >> 5) & 0x1)
/* Revision (4:0) */
#define SSC_ID_REV (0x1f)
#define SSC_ID_REV_GET(val) ((((val) & SSC_ID_REV) >> 0) & 0x1f)
/*******************************************************************************
* MCON Register
******************************************************************************/
/* Echo Mode (24) */
#define SSC_MCON_EM (0x1 << 24)
#define SSC_MCON_EM_VAL(val) (((val) & 0x1) << 24)
#define SSC_MCON_EM_GET(val) ((((val) & SSC_MCON_EM) >> 24) & 0x1)
#define SSC_MCON_EM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_EM) | (((val) & 0x1) << 24))
/* Idle Bit Value (23) */
#define SSC_MCON_IDLE (0x1 << 23)
#define SSC_MCON_IDLE_VAL(val) (((val) & 0x1) << 23)
#define SSC_MCON_IDLE_GET(val) ((((val) & SSC_MCON_IDLE) >> 23) & 0x1)
#define SSC_MCON_IDLE_SET(reg,val) (reg) = ((reg & ~SSC_MCON_IDLE) | (((val) & 0x1) << 23))
/* Enable Byte Valid Control (22) */
#define SSC_MCON_ENBV (0x1 << 22)
#define SSC_MCON_ENBV_VAL(val) (((val) & 0x1) << 22)
#define SSC_MCON_ENBV_GET(val) ((((val) & SSC_MCON_ENBV) >> 22) & 0x1)
#define SSC_MCON_ENBV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_ENBV) | (((val) & 0x1) << 22))
/* Data Width Selection (20:16) */
#define SSC_MCON_BM (0x1f << 16)
#define SSC_MCON_BM_VAL(val) (((val) & 0x1f) << 16)
#define SSC_MCON_BM_GET(val) ((((val) & SSC_MCON_BM) >> 16) & 0x1f)
#define SSC_MCON_BM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_BM) | (((val) & 0x1f) << 16))
/* Receive Underflow Error Enable (12) */
#define SSC_MCON_RUEN (0x1 << 12)
#define SSC_MCON_RUEN_VAL(val) (((val) & 0x1) << 12)
#define SSC_MCON_RUEN_GET(val) ((((val) & SSC_MCON_RUEN) >> 12) & 0x1)
#define SSC_MCON_RUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RUEN) | (((val) & 0x1) << 12))
/* Transmit Underflow Error Enable (11) */
#define SSC_MCON_TUEN (0x1 << 11)
#define SSC_MCON_TUEN_VAL(val) (((val) & 0x1) << 11)
#define SSC_MCON_TUEN_GET(val) ((((val) & SSC_MCON_TUEN) >> 11) & 0x1)
#define SSC_MCON_TUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TUEN) | (((val) & 0x1) << 11))
/* Abort Error Enable (10) */
#define SSC_MCON_AEN (0x1 << 10)
#define SSC_MCON_AEN_VAL(val) (((val) & 0x1) << 10)
#define SSC_MCON_AEN_GET(val) ((((val) & SSC_MCON_AEN) >> 10) & 0x1)
#define SSC_MCON_AEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_AEN) | (((val) & 0x1) << 10))
/* Receive Overflow Error Enable (9) */
#define SSC_MCON_REN (0x1 << 9)
#define SSC_MCON_REN_VAL(val) (((val) & 0x1) << 9)
#define SSC_MCON_REN_GET(val) ((((val) & SSC_MCON_REN) >> 9) & 0x1)
#define SSC_MCON_REN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_REN) | (((val) & 0x1) << 9))
/* Transmit Overflow Error Enable (8) */
#define SSC_MCON_TEN (0x1 << 8)
#define SSC_MCON_TEN_VAL(val) (((val) & 0x1) << 8)
#define SSC_MCON_TEN_GET(val) ((((val) & SSC_MCON_TEN) >> 8) & 0x1)
#define SSC_MCON_TEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TEN) | (((val) & 0x1) << 8))
/* Loop Back Control (7) */
#define SSC_MCON_LB (0x1 << 7)
#define SSC_MCON_LB_VAL(val) (((val) & 0x1) << 7)
#define SSC_MCON_LB_GET(val) ((((val) & SSC_MCON_LB) >> 7) & 0x1)
#define SSC_MCON_LB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_LB) | (((val) & 0x1) << 7))
/* Clock Polarity Control (6) */
#define SSC_MCON_PO (0x1 << 6)
#define SSC_MCON_PO_VAL(val) (((val) & 0x1) << 6)
#define SSC_MCON_PO_GET(val) ((((val) & SSC_MCON_PO) >> 6) & 0x1)
#define SSC_MCON_PO_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PO) | (((val) & 0x1) << 6))
/* Clock Phase Control (5) */
#define SSC_MCON_PH (0x1 << 5)
#define SSC_MCON_PH_VAL(val) (((val) & 0x1) << 5)
#define SSC_MCON_PH_GET(val) ((((val) & SSC_MCON_PH) >> 5) & 0x1)
#define SSC_MCON_PH_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PH) | (((val) & 0x1) << 5))
/* Heading Control (4) */
#define SSC_MCON_HB (0x1 << 4)
#define SSC_MCON_HB_VAL(val) (((val) & 0x1) << 4)
#define SSC_MCON_HB_GET(val) ((((val) & SSC_MCON_HB) >> 4) & 0x1)
#define SSC_MCON_HB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_HB) | (((val) & 0x1) << 4))
/* Chip Select Enable (3) */
#define SSC_MCON_CSBEN (0x1 << 3)
#define SSC_MCON_CSBEN_VAL(val) (((val) & 0x1) << 3)
#define SSC_MCON_CSBEN_GET(val) ((((val) & SSC_MCON_CSBEN) >> 3) & 0x1)
#define SSC_MCON_CSBEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBEN) | (((val) & 0x1) << 3))
/* Chip Select Invert (2) */
#define SSC_MCON_CSBINV (0x1 << 2)
#define SSC_MCON_CSBINV_VAL(val) (((val) & 0x1) << 2)
#define SSC_MCON_CSBINV_GET(val) ((((val) & SSC_MCON_CSBINV) >> 2) & 0x1)
#define SSC_MCON_CSBINV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBINV) | (((val) & 0x1) << 2))
/* Receive Off (1) */
#define SSC_MCON_RXOFF (0x1 << 1)
#define SSC_MCON_RXOFF_VAL(val) (((val) & 0x1) << 1)
#define SSC_MCON_RXOFF_GET(val) ((((val) & SSC_MCON_RXOFF) >> 1) & 0x1)
#define SSC_MCON_RXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RXOFF) | (((val) & 0x1) << 1))
/* Transmit Off (0) */
#define SSC_MCON_TXOFF (0x1)
#define SSC_MCON_TXOFF_VAL(val) (((val) & 0x1) << 0)
#define SSC_MCON_TXOFF_GET(val) ((((val) & SSC_MCON_TXOFF) >> 0) & 0x1)
#define SSC_MCON_TXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TXOFF) | (((val) & 0x1) << 0))
/*******************************************************************************
* STATE Register
******************************************************************************/
/* Receive End-of-Message (31) */
#define SSC_STATE_RXEOM (0x1 << 31)
#define SSC_STATE_RXEOM_GET(val) ((((val) & SSC_STATE_RXEOM) >> 31) & 0x1)
/* Receive Byte Valid (30:28) */
#define SSC_STATE_RXBV (0x7 << 28)
#define SSC_STATE_RXBV_GET(val) ((((val) & SSC_STATE_RXBV) >> 28) & 0x7)
/* Transmit End-of-Message (27) */
#define SSC_STATE_TXEOM (0x1 << 27)
#define SSC_STATE_TXEOM_GET(val) ((((val) & SSC_STATE_TXEOM) >> 27) & 0x1)
/* Transmit Byte Valid (26:24) */
#define SSC_STATE_TXBV (0x7 << 24)
#define SSC_STATE_TXBV_GET(val) ((((val) & SSC_STATE_TXBV) >> 24) & 0x7)
/* Bit Count Field (20:16) */
#define SSC_STATE_BC (0x1f << 16)
#define SSC_STATE_BC_GET(val) ((((val) & SSC_STATE_BC) >> 16) & 0x1f)
/* Busy Flag (13) */
#define SSC_STATE_BSY (0x1 << 13)
#define SSC_STATE_BSY_GET(val) ((((val) & SSC_STATE_BSY) >> 13) & 0x1)
/* Receive Underflow Error Flag (12) */
#define SSC_STATE_RUE (0x1 << 12)
#define SSC_STATE_RUE_GET(val) ((((val) & SSC_STATE_RUE) >> 12) & 0x1)
/* Transmit Underflow Error Flag (11) */
#define SSC_STATE_TUE (0x1 << 11)
#define SSC_STATE_TUE_GET(val) ((((val) & SSC_STATE_TUE) >> 11) & 0x1)
/* Abort Error Flag (10) */
#define SSC_STATE_AE (0x1 << 10)
#define SSC_STATE_AE_GET(val) ((((val) & SSC_STATE_AE) >> 10) & 0x1)
/* Receive Error Flag (9) */
#define SSC_STATE_RE (0x1 << 9)
#define SSC_STATE_RE_GET(val) ((((val) & SSC_STATE_RE) >> 9) & 0x1)
/* Transmit Error Flag (8) */
#define SSC_STATE_TE (0x1 << 8)
#define SSC_STATE_TE_GET(val) ((((val) & SSC_STATE_TE) >> 8) & 0x1)
/* Mode Error Flag (7) */
#define SSC_STATE_ME (0x1 << 7)
#define SSC_STATE_ME_GET(val) ((((val) & SSC_STATE_ME) >> 7) & 0x1)
/* Slave Selected (2) */
#define SSC_STATE_SSEL (0x1 << 2)
#define SSC_STATE_SSEL_GET(val) ((((val) & SSC_STATE_SSEL) >> 2) & 0x1)
/* Master Select Bit (1) */
#define SSC_STATE_MS (0x1 << 1)
#define SSC_STATE_MS_GET(val) ((((val) & SSC_STATE_MS) >> 1) & 0x1)
/* Enable Bit (0) */
#define SSC_STATE_EN (0x1)
#define SSC_STATE_EN_GET(val) ((((val) & SSC_STATE_EN) >> 0) & 0x1)
/*******************************************************************************
* WHBSTATE Register
******************************************************************************/
/* Set Transmit Underflow Error Flag Bit (15) */
#define SSC_WHBSTATE_SETTUE (0x1 << 15)
#define SSC_WHBSTATE_SETTUE_VAL(val) (((val) & 0x1) << 15)
#define SSC_WHBSTATE_SETTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTUE) | (val) & 1) << 15)
/* Set Abort Error Flag Bit (14) */
#define SSC_WHBSTATE_SETAE (0x1 << 14)
#define SSC_WHBSTATE_SETAE_VAL(val) (((val) & 0x1) << 14)
#define SSC_WHBSTATE_SETAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETAE) | (val) & 1) << 14)
/* Set Receive Error Flag Bit (13) */
#define SSC_WHBSTATE_SETRE (0x1 << 13)
#define SSC_WHBSTATE_SETRE_VAL(val) (((val) & 0x1) << 13)
#define SSC_WHBSTATE_SETRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRE) | (val) & 1) << 13)
/* Set Transmit Error Flag Bit (12) */
#define SSC_WHBSTATE_SETTE (0x1 << 12)
#define SSC_WHBSTATE_SETTE_VAL(val) (((val) & 0x1) << 12)
#define SSC_WHBSTATE_SETTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTE) | (val) & 1) << 12)
/* Clear Transmit Underflow Error Flag Bit (11) */
#define SSC_WHBSTATE_CLRTUE (0x1 << 11)
#define SSC_WHBSTATE_CLRTUE_VAL(val) (((val) & 0x1) << 11)
#define SSC_WHBSTATE_CLRTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTUE) | (val) & 1) << 11)
/* Clear Abort Error Flag Bit (10) */
#define SSC_WHBSTATE_CLRAE (0x1 << 10)
#define SSC_WHBSTATE_CLRAE_VAL(val) (((val) & 0x1) << 10)
#define SSC_WHBSTATE_CLRAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRAE) | (val) & 1) << 10)
/* Clear Receive Error Flag Bit (9) */
#define SSC_WHBSTATE_CLRRE (0x1 << 9)
#define SSC_WHBSTATE_CLRRE_VAL(val) (((val) & 0x1) << 9)
#define SSC_WHBSTATE_CLRRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRE) | (val) & 1) << 9)
/* Clear Transmit Error Flag Bit (8) */
#define SSC_WHBSTATE_CLRTE (0x1 << 8)
#define SSC_WHBSTATE_CLRTE_VAL(val) (((val) & 0x1) << 8)
#define SSC_WHBSTATE_CLRTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTE) | (val) & 1) << 8)
/* Set Mode Error Flag Bit (7) */
#define SSC_WHBSTATE_SETME (0x1 << 7)
#define SSC_WHBSTATE_SETME_VAL(val) (((val) & 0x1) << 7)
#define SSC_WHBSTATE_SETME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETME) | (val) & 1) << 7)
/* Clear Mode Error Flag Bit (6) */
#define SSC_WHBSTATE_CLRME (0x1 << 6)
#define SSC_WHBSTATE_CLRME_VAL(val) (((val) & 0x1) << 6)
#define SSC_WHBSTATE_CLRME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRME) | (val) & 1) << 6)
/* Set Receive Underflow Error Bit (5) */
#define SSC_WHBSTATE_SETRUE (0x1 << 5)
#define SSC_WHBSTATE_SETRUE_VAL(val) (((val) & 0x1) << 5)
#define SSC_WHBSTATE_SETRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRUE) | (val) & 1) << 5)
/* Clear Receive Underflow Error Bit (4) */
#define SSC_WHBSTATE_CLRRUE (0x1 << 4)
#define SSC_WHBSTATE_CLRRUE_VAL(val) (((val) & 0x1) << 4)
#define SSC_WHBSTATE_CLRRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRUE) | (val) & 1) << 4)
/* Set Master Select Bit (3) */
#define SSC_WHBSTATE_SETMS (0x1 << 3)
#define SSC_WHBSTATE_SETMS_VAL(val) (((val) & 0x1) << 3)
#define SSC_WHBSTATE_SETMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETMS) | (val) & 1) << 3)
/* Clear Master Select Bit (2) */
#define SSC_WHBSTATE_CLRMS (0x1 << 2)
#define SSC_WHBSTATE_CLRMS_VAL(val) (((val) & 0x1) << 2)
#define SSC_WHBSTATE_CLRMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRMS) | (val) & 1) << 2)
/* Set Enable Bit (1) */
#define SSC_WHBSTATE_SETEN (0x1 << 1)
#define SSC_WHBSTATE_SETEN_VAL(val) (((val) & 0x1) << 1)
#define SSC_WHBSTATE_SETEN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETEN) | (val) & 1) << 1)
/* Clear Enable Bit (0) */
#define SSC_WHBSTATE_CLREN (0x1)
#define SSC_WHBSTATE_CLREN_VAL(val) (((val) & 0x1) << 0)
#define SSC_WHBSTATE_CLREN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLREN) | (val) & 1) << 0)
/*******************************************************************************
* TB Register
******************************************************************************/
/* Transmit Data Register Value (31:0) */
#define SSC_TB_TB_VAL (0xFFFFFFFFL)
#define SSC_TB_TB_VAL_VAL(val) (((val) & 0xFFFFFFFFL) << 0)
#define SSC_TB_TB_VAL_GET(val) ((((val) & SSC_TB_TB_VAL) >> 0) & 0xFFFFFFFFL)
#define SSC_TB_TB_VAL_SET(reg,val) (reg) = ((reg & ~SSC_TB_TB_VAL) | (((val) & 0xFFFFFFFFL) << 0))
/*******************************************************************************
* RB Register
******************************************************************************/
/* Receive Data Register Value (31:0) */
#define SSC_RB_RB_VAL (0xFFFFFFFFL)
#define SSC_RB_RB_VAL_GET(val) ((((val) & SSC_RB_RB_VAL) >> 0) & 0xFFFFFFFFL)
/*******************************************************************************
* FSTAT Register
******************************************************************************/
/* Transmit FIFO Filling Level (13:8) */
#define SSC_FSTAT_TXFFL (0x3f << 8)
#define SSC_FSTAT_TXFFL_GET(val) ((((val) & SSC_FSTAT_TXFFL) >> 8) & 0x3f)
/* Receive FIFO Filling Level (5:0) */
#define SSC_FSTAT_RXFFL (0x3f)
#define SSC_FSTAT_RXFFL_GET(val) ((((val) & SSC_FSTAT_RXFFL) >> 0) & 0x3f)
/*******************************************************************************
* PISEL Register
******************************************************************************/
/* Slave Mode Clock Input Select (2) */
#define SSC_PISEL_CIS (0x1 << 2)
#define SSC_PISEL_CIS_VAL(val) (((val) & 0x1) << 2)
#define SSC_PISEL_CIS_GET(val) ((((val) & SSC_PISEL_CIS) >> 2) & 0x1)
#define SSC_PISEL_CIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_CIS) | (((val) & 0x1) << 2))
/* Slave Mode Receiver Input Select (1) */
#define SSC_PISEL_SIS (0x1 << 1)
#define SSC_PISEL_SIS_VAL(val) (((val) & 0x1) << 1)
#define SSC_PISEL_SIS_GET(val) ((((val) & SSC_PISEL_SIS) >> 1) & 0x1)
#define SSC_PISEL_SIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_SIS) | (((val) & 0x1) << 1))
/* Master Mode Receiver Input Select (0) */
#define SSC_PISEL_MIS (0x1)
#define SSC_PISEL_MIS_VAL(val) (((val) & 0x1) << 0)
#define SSC_PISEL_MIS_GET(val) ((((val) & SSC_PISEL_MIS) >> 0) & 0x1)
#define SSC_PISEL_MIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_MIS) | (((val) & 0x1) << 0))
/*******************************************************************************
* RXFCON Register
******************************************************************************/
/* Receive FIFO Interrupt Trigger Level (13:8) */
#define SSC_RXFCON_RXFITL (0x3f << 8)
#define SSC_RXFCON_RXFITL_VAL(val) (((val) & 0x3f) << 8)
#define SSC_RXFCON_RXFITL_GET(val) ((((val) & SSC_RXFCON_RXFITL) >> 8) & 0x3f)
#define SSC_RXFCON_RXFITL_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFITL) | (((val) & 0x3f) << 8))
/* Receive FIFO Flush (1) */
#define SSC_RXFCON_RXFLU (0x1 << 1)
#define SSC_RXFCON_RXFLU_VAL(val) (((val) & 0x1) << 1)
#define SSC_RXFCON_RXFLU_SET(reg,val) (reg) = (((reg & ~SSC_RXFCON_RXFLU) | (val) & 1) << 1)
/* Receive FIFO Enable (0) */
#define SSC_RXFCON_RXFEN (0x1)
#define SSC_RXFCON_RXFEN_VAL(val) (((val) & 0x1) << 0)
#define SSC_RXFCON_RXFEN_GET(val) ((((val) & SSC_RXFCON_RXFEN) >> 0) & 0x1)
#define SSC_RXFCON_RXFEN_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFEN) | (((val) & 0x1) << 0))
/*******************************************************************************
* TXFCON Register
******************************************************************************/
/* Transmit FIFO Interrupt Trigger Level (13:8) */
#define SSC_TXFCON_TXFITL (0x3f << 8)
#define SSC_TXFCON_TXFITL_VAL(val) (((val) & 0x3f) << 8)
#define SSC_TXFCON_TXFITL_GET(val) ((((val) & SSC_TXFCON_TXFITL) >> 8) & 0x3f)
#define SSC_TXFCON_TXFITL_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFITL) | (((val) & 0x3f) << 8))
/* Transmit FIFO Flush (1) */
#define SSC_TXFCON_TXFLU (0x1 << 1)
#define SSC_TXFCON_TXFLU_VAL(val) (((val) & 0x1) << 1)
#define SSC_TXFCON_TXFLU_SET(reg,val) (reg) = (((reg & ~SSC_TXFCON_TXFLU) | (val) & 1) << 1)
/* Transmit FIFO Enable (0) */
#define SSC_TXFCON_TXFEN (0x1)
#define SSC_TXFCON_TXFEN_VAL(val) (((val) & 0x1) << 0)
#define SSC_TXFCON_TXFEN_GET(val) ((((val) & SSC_TXFCON_TXFEN) >> 0) & 0x1)
#define SSC_TXFCON_TXFEN_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFEN) | (((val) & 0x1) << 0))
/*******************************************************************************
* BR Register
******************************************************************************/
/* Baudrate Timer Reload Register Value (15:0) */
#define SSC_BR_BR_VAL (0xffff)
#define SSC_BR_BR_VAL_VAL(val) (((val) & 0xffff) << 0)
#define SSC_BR_BR_VAL_GET(val) ((((val) & SSC_BR_BR_VAL) >> 0) & 0xffff)
#define SSC_BR_BR_VAL_SET(reg,val) (reg) = ((reg & ~SSC_BR_BR_VAL) | (((val) & 0xffff) << 0))
/*******************************************************************************
* BRSTAT Register
******************************************************************************/
/* Baudrate Timer Register Value (15:0) */
#define SSC_BRSTAT_BT_VAL (0xffff)
#define SSC_BRSTAT_BT_VAL_GET(val) ((((val) & SSC_BRSTAT_BT_VAL) >> 0) & 0xffff)
/*******************************************************************************
* SFCON Register
******************************************************************************/
/* Pause Length (31:22) */
#define SSC_SFCON_PLEN (0x3ff << 22)
#define SSC_SFCON_PLEN_VAL(val) (((val) & 0x3ff) << 22)
#define SSC_SFCON_PLEN_GET(val) ((((val) & SSC_SFCON_PLEN) >> 22) & 0x3ff)
#define SSC_SFCON_PLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_PLEN) | (((val) & 0x3ff) << 22))
/* Stop After Pause (20) */
#define SSC_SFCON_STOP (0x1 << 20)
#define SSC_SFCON_STOP_VAL(val) (((val) & 0x1) << 20)
#define SSC_SFCON_STOP_GET(val) ((((val) & SSC_SFCON_STOP) >> 20) & 0x1)
#define SSC_SFCON_STOP_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_STOP) | (((val) & 0x1) << 20))
/* Idle Clock Configuration (19:18) */
#define SSC_SFCON_ICLK (0x3 << 18)
#define SSC_SFCON_ICLK_VAL(val) (((val) & 0x3) << 18)
#define SSC_SFCON_ICLK_GET(val) ((((val) & SSC_SFCON_ICLK) >> 18) & 0x3)
#define SSC_SFCON_ICLK_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_ICLK) | (((val) & 0x3) << 18))
/* Idle Data Configuration (17:16) */
#define SSC_SFCON_IDAT (0x3 << 16)
#define SSC_SFCON_IDAT_VAL(val) (((val) & 0x3) << 16)
#define SSC_SFCON_IDAT_GET(val) ((((val) & SSC_SFCON_IDAT) >> 16) & 0x3)
#define SSC_SFCON_IDAT_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IDAT) | (((val) & 0x3) << 16))
/* Data Length (15:4) */
#define SSC_SFCON_DLEN (0xfff << 4)
#define SSC_SFCON_DLEN_VAL(val) (((val) & 0xfff) << 4)
#define SSC_SFCON_DLEN_GET(val) ((((val) & SSC_SFCON_DLEN) >> 4) & 0xfff)
#define SSC_SFCON_DLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_DLEN) | (((val) & 0xfff) << 4))
/* Enable Interrupt After Pause (3) */
#define SSC_SFCON_IAEN (0x1 << 3)
#define SSC_SFCON_IAEN_VAL(val) (((val) & 0x1) << 3)
#define SSC_SFCON_IAEN_GET(val) ((((val) & SSC_SFCON_IAEN) >> 3) & 0x1)
#define SSC_SFCON_IAEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IAEN) | (((val) & 0x1) << 3))
/* Enable Interrupt Before Pause (2) */
#define SSC_SFCON_IBEN (0x1 << 2)
#define SSC_SFCON_IBEN_VAL(val) (((val) & 0x1) << 2)
#define SSC_SFCON_IBEN_GET(val) ((((val) & SSC_SFCON_IBEN) >> 2) & 0x1)
#define SSC_SFCON_IBEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IBEN) | (((val) & 0x1) << 2))
/* Serial Frame Enable (0) */
#define SSC_SFCON_SFEN (0x1)
#define SSC_SFCON_SFEN_VAL(val) (((val) & 0x1) << 0)
#define SSC_SFCON_SFEN_GET(val) ((((val) & SSC_SFCON_SFEN) >> 0) & 0x1)
#define SSC_SFCON_SFEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_SFEN) | (((val) & 0x1) << 0))
/*******************************************************************************
* SFSTAT Register
******************************************************************************/
/* Pause Count (31:22) */
#define SSC_SFSTAT_PCNT (0x3ff << 22)
#define SSC_SFSTAT_PCNT_GET(val) ((((val) & SSC_SFSTAT_PCNT) >> 22) & 0x3ff)
/* Data Bit Count (15:4) */
#define SSC_SFSTAT_DCNT (0xfff << 4)
#define SSC_SFSTAT_DCNT_GET(val) ((((val) & SSC_SFSTAT_DCNT) >> 4) & 0xfff)
/* Pause Busy (1) */
#define SSC_SFSTAT_PBSY (0x1 << 1)
#define SSC_SFSTAT_PBSY_GET(val) ((((val) & SSC_SFSTAT_PBSY) >> 1) & 0x1)
/* Data Busy (0) */
#define SSC_SFSTAT_DBSY (0x1)
#define SSC_SFSTAT_DBSY_GET(val) ((((val) & SSC_SFSTAT_DBSY) >> 0) & 0x1)
/*******************************************************************************
* GPOCON Register
******************************************************************************/
/* Output OUTn Is Chip Select (15:8) */
#define SSC_GPOCON_ISCSBN (0xff << 8)
#define SSC_GPOCON_ISCSBN_VAL(val) (((val) & 0xff) << 8)
#define SSC_GPOCON_ISCSBN_GET(val) ((((val) & SSC_GPOCON_ISCSBN) >> 8) & 0xff)
#define SSC_GPOCON_ISCSBN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_ISCSBN) | (((val) & 0xff) << 8))
/* Invert Output OUTn (7:0) */
#define SSC_GPOCON_INVOUTN (0xff)
#define SSC_GPOCON_INVOUTN_VAL(val) (((val) & 0xff) << 0)
#define SSC_GPOCON_INVOUTN_GET(val) ((((val) & SSC_GPOCON_INVOUTN) >> 0) & 0xff)
#define SSC_GPOCON_INVOUTN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_INVOUTN) | (((val) & 0xff) << 0))
/*******************************************************************************
* GPOSTAT Register
******************************************************************************/
/* Output Register Bit n (7:0) */
#define SSC_GPOSTAT_OUTN (0xff)
#define SSC_GPOSTAT_OUTN_GET(val) ((((val) & SSC_GPOSTAT_OUTN) >> 0) & 0xff)
/*******************************************************************************
* WHBGPOSTAT
******************************************************************************/
/* Set Output Register Bit n (15:8) */
#define SSC_WHBGPOSTAT_SETOUTN (0xff << 8)
#define SSC_WHBGPOSTAT_SETOUTN_VAL(val) (((val) & 0xff) << 8)
#define SSC_WHBGPOSTAT_SETOUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_SETOUTN) | (val) & 1) << 8)
/* Clear Output Register Bit n (7:0) */
#define SSC_WHBGPOSTAT_CLROUTN (0xff)
#define SSC_WHBGPOSTAT_CLROUTN_VAL(val) (((val) & 0xff) << 0)
#define SSC_WHBGPOSTAT_CLROUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_CLROUTN) | (val) & 1) << 0)
/*******************************************************************************
* RXREQ Register
******************************************************************************/
/* Receive Count Value (15:0) */
#define SSC_RXREQ_RXCNT (0xffff)
#define SSC_RXREQ_RXCNT_VAL(val) (((val) & 0xffff) << 0)
#define SSC_RXREQ_RXCNT_GET(val) ((((val) & SSC_RXREQ_RXCNT) >> 0) & 0xffff)
#define SSC_RXREQ_RXCNT_SET(reg,val) (reg) = ((reg & ~SSC_RXREQ_RXCNT) | (((val) & 0xffff) << 0))
/*******************************************************************************
* RXCNT Register
******************************************************************************/
/* Receive To Do Value (15:0) */
#define SSC_RXCNT_TODO (0xffff)
#define SSC_RXCNT_TODO_GET(val) ((((val) & SSC_RXCNT_TODO) >> 0) & 0xffff)
/*******************************************************************************
* DMA_CON Register
******************************************************************************/
/* Receive Class (3:2) */
#define SSC_DMA_CON_RXCLS (0x3 << 2)
#define SSC_DMA_CON_RXCLS_VAL(val) (((val) & 0x3) << 2)
#define SSC_DMA_CON_RXCLS_GET(val) ((((val) & SSC_DMA_CON_RXCLS) >> 2) & 0x3)
#define SSC_DMA_CON_RXCLS_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXCLS) | (((val) & 0x3) << 2))
/* Transmit Path On (1) */
#define SSC_DMA_CON_TXON (0x1 << 1)
#define SSC_DMA_CON_TXON_VAL(val) (((val) & 0x1) << 1)
#define SSC_DMA_CON_TXON_GET(val) ((((val) & SSC_DMA_CON_TXON) >> 1) & 0x1)
#define SSC_DMA_CON_TXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_TXON) | (((val) & 0x1) << 1))
/* Receive Path On (0) */
#define SSC_DMA_CON_RXON (0x1)
#define SSC_DMA_CON_RXON_VAL(val) (((val) & 0x1) << 0)
#define SSC_DMA_CON_RXON_GET(val) ((((val) & SSC_DMA_CON_RXON) >> 0) & 0x1)
#define SSC_DMA_CON_RXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXON) | (((val) & 0x1) << 0))
/*******************************************************************************
* IRNEN Register
******************************************************************************/
/* Frame End Interrupt Request Enable (3) */
#define SSC_IRNEN_F (0x1 << 3)
#define SSC_IRNEN_F_VAL(val) (((val) & 0x1) << 3)
#define SSC_IRNEN_F_GET(val) ((((val) & SSC_IRNEN_F) >> 3) & 0x1)
#define SSC_IRNEN_F_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_F) | (((val) & 0x1) << 3))
/* Error Interrupt Request Enable (2) */
#define SSC_IRNEN_E (0x1 << 2)
#define SSC_IRNEN_E_VAL(val) (((val) & 0x1) << 2)
#define SSC_IRNEN_E_GET(val) ((((val) & SSC_IRNEN_E) >> 2) & 0x1)
#define SSC_IRNEN_E_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_E) | (((val) & 0x1) << 2))
/* Receive Interrupt Request Enable (1) */
#define SSC_IRNEN_R (0x1 << 1)
#define SSC_IRNEN_R_VAL(val) (((val) & 0x1) << 1)
#define SSC_IRNEN_R_GET(val) ((((val) & SSC_IRNEN_R) >> 1) & 0x1)
#define SSC_IRNEN_R_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_R) | (((val) & 0x1) << 1))
/* Transmit Interrupt Request Enable (0) */
#define SSC_IRNEN_T (0x1)
#define SSC_IRNEN_T_VAL(val) (((val) & 0x1) << 0)
#define SSC_IRNEN_T_GET(val) ((((val) & SSC_IRNEN_T) >> 0) & 0x1)
#define SSC_IRNEN_T_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_T) | (((val) & 0x1) << 0))
/*******************************************************************************
* IRNICR Register
******************************************************************************/
/* Frame End Interrupt Request (3) */
#define SSC_IRNICR_F (0x1 << 3)
#define SSC_IRNICR_F_GET(val) ((((val) & SSC_IRNICR_F) >> 3) & 0x1)
/* Error Interrupt Request (2) */
#define SSC_IRNICR_E (0x1 << 2)
#define SSC_IRNICR_E_GET(val) ((((val) & SSC_IRNICR_E) >> 2) & 0x1)
/* Receive Interrupt Request (1) */
#define SSC_IRNICR_R (0x1 << 1)
#define SSC_IRNICR_R_GET(val) ((((val) & SSC_IRNICR_R) >> 1) & 0x1)
/* Transmit Interrupt Request (0) */
#define SSC_IRNICR_T (0x1)
#define SSC_IRNICR_T_GET(val) ((((val) & SSC_IRNICR_T) >> 0) & 0x1)
/*******************************************************************************
* IRNCR Register
******************************************************************************/
/* Frame End Interrupt Request (3) */
#define SSC_IRNCR_F (0x1 << 3)
#define SSC_IRNCR_F_GET(val) ((((val) & SSC_IRNCR_F) >> 3) & 0x1)
/* Error Interrupt Request (2) */
#define SSC_IRNCR_E (0x1 << 2)
#define SSC_IRNCR_E_GET(val) ((((val) & SSC_IRNCR_E) >> 2) & 0x1)
/* Receive Interrupt Request (1) */
#define SSC_IRNCR_R (0x1 << 1)
#define SSC_IRNCR_R_GET(val) ((((val) & SSC_IRNCR_R) >> 1) & 0x1)
/* Transmit Interrupt Request (0) */
#define SSC_IRNCR_T (0x1)
#define SSC_IRNCR_T_GET(val) ((((val) & SSC_IRNCR_T) >> 0) & 0x1)
#endif /* __SSC_H */

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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __STATUS_REG_H
#define __STATUS_REG_H
#define status_r32(reg) ltq_r32(&status->reg)
#define status_w32(val, reg) ltq_w32(val, &status->reg)
#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg)
/** STATUS register structure */
struct svip_reg_status {
unsigned long fuse_deu; /* 0x0000 */
unsigned long fuse_cpu; /* 0x0004 */
unsigned long fuse_pll; /* 0x0008 */
unsigned long chipid; /* 0x000C */
unsigned long config; /* 0x0010 */
unsigned long chip_loc; /* 0x0014 */
unsigned long fuse_spare; /* 0x0018 */
};
/*******************************************************************************
* Fuse for DEU Settings
******************************************************************************/
/* Fuse for Enabling the TRNG (6) */
#define STATUS_FUSE_DEU_TRNG (0x1 << 6)
#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1)
/* Fuse for Enabling the DES Submodule (5) */
#define STATUS_FUSE_DEU_DES (0x1 << 5)
#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1)
/* Fuse for Enabling the 3DES Submodule (4) */
#define STATUS_FUSE_DEU_3DES (0x1 << 4)
#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1)
/* Fuse for Enabling the AES Submodule (3) */
#define STATUS_FUSE_DEU_AES (0x1 << 3)
#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1)
/* Fuse for Enabling the HASH Submodule (2) */
#define STATUS_FUSE_DEU_HASH (0x1 << 2)
#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1)
/* Fuse for Enabling the ARC4 Submodule (1) */
#define STATUS_FUSE_DEU_ARC4 (0x1 << 1)
#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1)
/* Fuse for Enabling the DEU Module (0) */
#define STATUS_FUSE_DEU_DEU (0x1)
#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1)
/*******************************************************************************
* Fuse for CPU Settings
******************************************************************************/
/* Fuse for Enabling CPU5 (5) */
#define STATUS_FUSE_CPU_CPU5 (0x1 << 5)
#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1)
/* Fuse for Enabling the CPU4 (4) */
#define STATUS_FUSE_CPU_CPU4 (0x1 << 4)
#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1)
/* Fuse for Enabling the CPU3 (3) */
#define STATUS_FUSE_CPU_CPU3 (0x1 << 3)
#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1)
/* Fuse for Enabling the CPU2 (2) */
#define STATUS_FUSE_CPU_CPU2 (0x1 << 2)
#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1)
/* Fuse for Enabling the CPU1 (1) */
#define STATUS_FUSE_CPU_CPU1 (0x1 << 1)
#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1)
/* Fuse for Enabling the CPU0 (0) */
#define STATUS_FUSE_CPU_CPU0 (0x1)
#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1)
/*******************************************************************************
* Fuse for PLL Settings
******************************************************************************/
/* Fuse for Enabling PLL (7:0) */
#define STATUS_FUSE_PLL_PLL (0xff)
#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff)
/*******************************************************************************
* Chip Identification Register
******************************************************************************/
/* Chip Version Number (31:28) */
#define STATUS_CHIPID_VERSION (0xf << 28)
#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf)
/* Part Number (27:12) */
#define STATUS_CHIPID_PART_NUMBER (0xffff << 12)
#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff)
/* Manufacturer ID (11:1) */
#define STATUS_CHIPID_MANID (0x7ff << 1)
#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff)
/*******************************************************************************
* Chip Configuration Register
******************************************************************************/
/* Number of Analog Channels (8:5) */
#define STATUS_CONFIG_ANA_CHAN (0xf << 5)
#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf)
/* Clock Mode (4) */
#define STATUS_CONFIG_CLK_MODE (0x1 << 1)
#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1)
/* Subversion Number (3:0) */
#define STATUS_CONFIG_SUB_VERS (0xF)
#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF)
/*******************************************************************************
* Chip Location Register
******************************************************************************/
/* Chip Lot ID (31:16) */
#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16)
#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff)
/* Chip X Coordinate (15:8) */
#define STATUS_CHIP_LOC_CHIP_X (0xff << 8)
#define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff)
/* Chip Y Coordinate (7:0) */
#define STATUS_CHIP_LOC_CHIP_Y (0xff)
#define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff)
#endif

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/************************************************************************
*
* Copyright (c) 2007
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#ifndef __SVIP_DMA_H
#define __SVIP_DMA_H
#define LTQ_DMA_CH_ON 1
#define LTQ_DMA_CH_OFF 0
#define LTQ_DMA_CH_DEFAULT_WEIGHT 100;
#define DMA_OWN 1
#define CPU_OWN 0
#define DMA_MAJOR 250
/* Descriptors */
#define DMA_DESC_OWN_CPU 0x0
#define DMA_DESC_OWN_DMA 0x80000000
#define DMA_DESC_CPT_SET 0x40000000
#define DMA_DESC_SOP_SET 0x20000000
#define DMA_DESC_EOP_SET 0x10000000
struct rx_desc {
union {
struct {
#ifdef CONFIG_CPU_LITTLE_ENDIAN
volatile u32 data_length:16;
volatile u32 reserve2:7;
volatile u32 byte_offset:2;
volatile u32 reserve1:3;
volatile u32 eop:1;
volatile u32 sop:1;
volatile u32 c:1;
volatile u32 own:1;
#else
volatile u32 own:1;
volatile u32 c:1;
volatile u32 sop:1;
volatile u32 eop:1;
volatile u32 reserve1:3;
volatile u32 byte_offset:2;
volatile u32 reserve2:7;
volatile u32 data_length:16;
#endif
} field;
volatile u32 word;
} status;
volatile u32 data_pointer;
};
struct tx_desc {
union {
struct {
#ifdef CONFIG_CPU_LITTLE_ENDIAN
volatile u32 data_length:16;
volatile u32 reserved:7;
volatile u32 byte_offset:5;
volatile u32 eop:1;
volatile u32 sop:1;
volatile u32 c:1;
volatile u32 own:1;
#else
volatile u32 own:1;
volatile u32 c:1;
volatile u32 sop:1;
volatile u32 eop:1;
volatile u32 byte_offset:5;
volatile u32 reserved:7;
volatile u32 data_length:16;
#endif
} field;
volatile u32 word;
} status;
volatile u32 data_pointer;
};
/* DMA pseudo interrupts notified to switch driver */
#define RCV_INT 0x01
#define TX_BUF_FULL_INT 0x02
#define TRANSMIT_CPT_INT 0x04
#define CHANNEL_CLOSED 0x10
/* Parameters for switch DMA device */
#define DEFAULT_SW_CHANNEL_WEIGHT 3
#define DEFAULT_SW_PORT_WEIGHT 7
#define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
#define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
#define DEFAULT_SW_TX_CHANNEL_NUM 4
#define DEFAULT_SW_RX_CHANNEL_NUM 4
#define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20
#define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20
/* Parameters for SSC DMA device */
#define DEFAULT_SSC_CHANNEL_WEIGHT 3
#define DEFAULT_SSC_PORT_WEIGHT 7
#define DEFAULT_SSC_TX_CHANNEL_CLASS 3
#define DEFAULT_SSC_RX_CHANNEL_CLASS 0
#define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
#define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
#define DEFAULT_SSC0_TX_CHANNEL_NUM 1
#define DEFAULT_SSC0_RX_CHANNEL_NUM 1
#define DEFAULT_SSC1_TX_CHANNEL_NUM 1
#define DEFAULT_SSC1_RX_CHANNEL_NUM 1
#define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10
#define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10
/* Parameters for memory DMA device */
#define DEFAULT_MEM_CHANNEL_WEIGHT 3
#define DEFAULT_MEM_PORT_WEIGHT 7
#define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
#define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
#define DEFAULT_MEM_TX_CHANNEL_NUM 1
#define DEFAULT_MEM_RX_CHANNEL_NUM 1
#define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2
#define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2
/* Parameters for DEU DMA device */
#define DEFAULT_DEU_CHANNEL_WEIGHT 1
#define DEFAULT_DEU_PORT_WEIGHT 1
#define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
#define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
#define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20
#define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20
#define DMA_DESCR_NUM 30 /* number of descriptors per channel */
enum dma_dir_t {
DIR_RX = 0,
DIR_TX = 1,
};
struct dma_device_info;
struct dma_channel_info {
/*Pointer to the peripheral device who is using this channel*/
/*const*/ struct dma_device_info *dma_dev;
/*direction*/
const enum dma_dir_t dir; /*RX or TX*/
/*class for this channel for QoS*/
int pri;
/*irq number*/
const int irq;
/*relative channel number*/
const int rel_chan_no;
/*absolute channel number*/
int abs_chan_no;
/*specify byte_offset*/
int byte_offset;
int tx_weight;
/*descriptor parameter*/
int desc_base;
int desc_len;
int curr_desc;
int prev_desc;/*only used if it is a tx channel*/
/*weight setting for WFQ algorithm*/
int weight;
int default_weight;
int packet_size;
/*status of this channel*/
int control; /*on or off*/
int xfer_cnt;
int dur; /*descriptor underrun*/
/**optional information for the upper layer devices*/
void *opt[DMA_DESCR_NUM];
/*channel operations*/
int (*open)(struct dma_channel_info *ch);
int (*close)(struct dma_channel_info *ch);
int (*reset)(struct dma_channel_info *ch);
void (*enable_irq)(struct dma_channel_info *ch);
void (*disable_irq)(struct dma_channel_info *ch);
};
struct dma_device_info {
/*device name of this peripheral*/
const char device_name[16];
const int max_rx_chan_num;
const int max_tx_chan_num;
int drop_enable;
int reserved;
int tx_burst_len;
int rx_burst_len;
int tx_weight;
int current_tx_chan;
int current_rx_chan;
int num_tx_chan;
int num_rx_chan;
int tx_endianness_mode;
int rx_endianness_mode;
struct dma_channel_info *tx_chan[4];
struct dma_channel_info *rx_chan[4];
/*functions, optional*/
u8 *(*buffer_alloc)(int len,int *offset, void **opt);
void (*buffer_free)(u8 *dataptr, void *opt);
int (*intr_handler)(struct dma_device_info *dma_dev, int status);
/* used by peripheral driver only */
void *priv;
};
struct dma_device_info *dma_device_reserve(char *dev_name);
int dma_device_release(struct dma_device_info *dma_dev);
int dma_device_register(struct dma_device_info *dma_dev);
int dma_device_unregister(struct dma_device_info *dma_dev);
int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt);
int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr,
int len, void *opt);
#endif

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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2010 Lantiq
*/
#ifndef __SVIP_IRQ_H
#define __SVIP_IRQ_H
#define IM_NUM 6
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160)
#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2)
#endif

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/************************************************************************
*
* Copyright (c) 2007
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#ifndef __SVIP_MUX_H
#define __SVIP_MUX_H
#define LTQ_MUX_P0_PINS 20
#define LTQ_MUX_P1_PINS 20
#define LTQ_MUX_P2_PINS 19
#define LTQ_MUX_P3_PINS 20
#define LTQ_MUX_P4_PINS 24
struct ltq_mux_pin {
int dirin;
int puen;
int altsel0;
int altsel1;
};
struct ltq_mux_settings {
const struct ltq_mux_pin *mux_p0;
const struct ltq_mux_pin *mux_p1;
const struct ltq_mux_pin *mux_p2;
const struct ltq_mux_pin *mux_p3;
const struct ltq_mux_pin *mux_p4;
};
#define LTQ_MUX_P0_19_EXINT16 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_19 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_18_EJ_BRKIN { 1, 0, 0, 0 }
#define LTQ_MUX_P0_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_18_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_17_EXINT10 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_17 { 0, 0, 0, 0 }
#define LTQ_MUX_P0_17_ASC1_RXD { 1, 0, 1, 0 }
#define LTQ_MUX_P0_16_EXINT9 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_16 { 0, 0, 0, 0 }
#define LTQ_MUX_P0_16_ASC1_TXD { 0, 0, 1, 0 }
#define LTQ_MUX_P0_15_EXINT8 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_15 { 0, 0, 0, 0 }
#define LTQ_MUX_P0_15_ASC0_RXD { 1, 0, 1, 0 }
#define LTQ_MUX_P0_14_EXINT7 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_14 { 0, 0, 0, 0 }
#define LTQ_MUX_P0_14_ASC0_TXD { 1, 0, 1, 0 }
#define LTQ_MUX_P0_13_SSC0_CS7 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_13_EXINT6 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_13 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_13_SSC1_CS7 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_13_SSC1_INT { 0, 0, 1, 1 }
#define LTQ_MUX_P0_12_SSC0_CS6 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_12_EXINT5 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_12 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_12_SSC1_CS6 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_11_SSC0_CS5 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_11_EXINT4 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_11 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_11_SSC1_CS5 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_10_SSC0_CS4 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_10_EXINT3 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_10_SSC1_CS4 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_9_SSC0_CS3 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_9_EXINT2 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_9_SSC1_CS3 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_8_SSC0_CS2 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_8_EXINT1 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_8_SSC1_CS2 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_7_SSC0_CS1 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_7_EXINT0 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_7_SSC1_CS1 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_7_SSC1_CS0 { 1, 0, 0, 1 }
#define LTQ_MUX_P0_7_SSC2_CS0 { 1, 0, 1, 1 }
#define LTQ_MUX_P0_6_SSC0_CS0 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_6_SSC1_CS0 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_5_SSC1_SCLK { 0, 0, 0, 0 }
#define LTQ_MUX_P0_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_5_SSC2_CLK { 1, 0, 0, 1 }
#define LTQ_MUX_P0_4_SSC1_MRST { 1, 0, 0, 0 }
#define LTQ_MUX_P0_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_4_SSC2_MRST { 0, 0, 0, 1 }
#define LTQ_MUX_P0_3_SSC1_MTSR { 0, 0, 0, 0 }
#define LTQ_MUX_P0_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_3_SSC2_MTSR { 0, 0, 0, 1 }
#define LTQ_MUX_P0_2_SSC0_SCLK { 0, 0, 0, 0 }
#define LTQ_MUX_P0_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_1_SSC0_MRST { 1, 0, 0, 0 }
#define LTQ_MUX_P0_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_0_SSC0_MTSR { 0, 0, 0, 0 }
#define LTQ_MUX_P0_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_0_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_19_PCM3_TC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P1_19_EXINT15 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_19 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_18_PCM3_FSC { 0, 0, 0, 0 }
#define LTQ_MUX_P1_18_EXINT11 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_17_PCM3_PCL { 0, 0, 0, 0 }
#define LTQ_MUX_P1_17_EXINT12 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_17 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_16_PCM3_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_16_EXINT13 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_16 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_15_PCM3_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_15_EXINT14 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_15 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_14_PCM2_TC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P1_14 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_14_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_13_PCM2_FSC { 0, 0, 0, 0 }
#define LTQ_MUX_P1_13 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_13_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_12_PCM2_PCL { 0, 0, 0, 0 }
#define LTQ_MUX_P1_12 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_12_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_11_PCM2_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_11 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_11_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_10_PCM2_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_10_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_9_PCM1_TC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P1_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_9_IN { 0, 0, 1, 0 }
#define LTQ_MUX_P1_8_PCM1_FSC { 0, 0, 0, 0 }
#define LTQ_MUX_P1_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_8_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_7_PCM1_PCL { 0, 0, 0, 0 }
#define LTQ_MUX_P1_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_7_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_6_PCM1_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_5_PCM1_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_4_PCM0_TC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P1_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_3_PCM0_FSC { 0, 0, 0, 0 }
#define LTQ_MUX_P1_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_2_PCM0_PCL { 0, 0, 0, 0 }
#define LTQ_MUX_P1_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_1_PCM0_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_0_PCM0_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_0_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_18_EBU_BC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_18_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_17_EBU_BC0 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_17 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_17_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_16_EBU_RDBY { 1, 0, 0, 0 }
#define LTQ_MUX_P2_16 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_16_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_15_EBU_WAIT { 1, 0, 0, 0 }
#define LTQ_MUX_P2_15 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_15_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_14_EBU_ALE { 0, 0, 0, 0 }
#define LTQ_MUX_P2_14 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_14_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_13_EBU_WR { 0, 0, 0, 0 }
#define LTQ_MUX_P2_13 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_13_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_12_EBU_RD { 0, 0, 0, 0 }
#define LTQ_MUX_P2_12 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_12_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_11_EBU_A11 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_11 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_11_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_10_EBU_A10 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_10_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_9_EBU_A9 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_9_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_8_EBU_A8 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_8_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_7_EBU_A7 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_7_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_6_EBU_A6 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_5_EBU_A5 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_4_EBU_A4 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_3_EBU_A3 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_2_EBU_A2 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_1_EBU_A1 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_0_EBU_A0 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_0_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_19_EBU_CS3 { 0, 0, 0, 0 }
#define LTQ_MUX_P3_19 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_19_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_18_EBU_CS2 { 0, 0, 0, 0 }
#define LTQ_MUX_P3_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_18_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_17_EBU_CS1 { 0, 0, 0, 0 }
#define LTQ_MUX_P3_17 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_17_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_16_EBU_CS0 { 0, 0, 0, 0 }
#define LTQ_MUX_P3_16 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_16_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_15_EBU_AD15 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_15 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_15_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_14_EBU_AD14 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_14 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_14_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_13_EBU_AD13 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_13 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_13_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_12_EBU_AD12 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_12 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_12_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_11_EBU_AD11 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_11 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_11_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_10_EBU_AD10 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_10_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_9_EBU_AD9 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_9_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_8_EBU_AD8 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_8_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_7_EBU_AD7 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_7_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_6_EBU_AD6 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_5_EBU_AD5 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_4_EBU_AD4 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_3_EBU_AD3 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_2_EBU_AD2 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_1_EBU_AD1 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_0_EBU_AD0 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_0_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_23_SSLIC7_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_23 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_23_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_22_SSLIC7_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_22 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_22_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_21_SSLIC7_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_21 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_21_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_20_SSLIC6_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_20 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_20_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_19_SSLIC6_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_19 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_19_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_18_SSLIC6_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_18_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_17_SSLIC5_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_17 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_17_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_16_SSLIC5_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_16 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_16_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_15_SSLIC5_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_15 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_15_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_14_SSLIC4_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_14 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_14_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_13_SSLIC4_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_13 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_13_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_12_SSLIC4_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_12 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_12_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_11_SSLIC3_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_11 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_11_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_10_SSLIC3_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_10_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_9_SSLIC3_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_9_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_8_SSLIC2_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_8_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_7_SSLIC2_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_7_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_6_SSLIC2_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_5_SSLIC1_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_4_SSLIC1_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_3_SSLIC1_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_2_SSLIC0_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_1_SSLIC0_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_0_SSLIC0_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_0_IN { 1, 0, 1, 0 }
#endif

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target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h Normal file
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/************************************************************************
*
* Copyright (c) 2007
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#ifndef __SVIP_PMS_H
#define __SVIP_PMS_H
void svip_sys1_clk_enable(u32 mask);
int svip_sys1_clk_is_enabled(u32 mask);
void svip_sys2_clk_enable(u32 mask);
int svip_sys2_clk_is_enabled(u32 mask);
#endif

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target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h Normal file
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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __SYS0_REG_H
#define __SYS0_REG_H
#define sys0_r32(reg) ltq_r32(&sys0->reg)
#define sys0_w32(val, reg) ltq_w32(val, &sys0->reg)
#define sys0_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys0->reg)
/** SYS0 register structure */
struct svip_reg_sys0 {
unsigned long sr; /* 0x0000 */
unsigned long bcr; /* 0x0004 */
unsigned long pll1cr; /* 0x0008 */
unsigned long pll2cr; /* 0x000c */
unsigned long tscr; /* 0x0010 */
unsigned long phyclkr; /* 0x0014 */
};
/*******************************************************************************
* SYS0 Status Register
******************************************************************************/
/* Endian select pin (31) */
#define SYS0_SR_ESEL (0x1 << 31)
#define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1)
/* Boot mode pins (27:24) */
#define SYS0_SR_BMODE (0xf << 24)
#define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf)
/* PLL2 Lock (18) */
#define SYS0_SR_PLL2LOCK (0x1 << 18)
#define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1)
/* PLL1 Lock (17) */
#define SYS0_SR_PLL1LOCK (0x1 << 17)
#define SYS0_SR_PLL1LOCK_GET(val) ((((val) & SYS0_SR_PLL1LOCK) >> 17) & 0x1)
/* Discrete Timing Oscillator Lock (16) */
#define SYS0_SR_DTOLOCK (0x1 << 16)
#define SYS0_SR_DTOLOCK_GET(val) ((((val) & SYS0_SR_DTOLOCK) >> 16) & 0x1)
/* Hardware Reset Indication (1) */
#define SYS0_SR_HRSTIN (0x1 << 1)
#define SYS0_SR_HRSTIN_VAL(val) (((val) & 0x1) << 1)
#define SYS0_SR_HRSTIN_GET(val) ((((val) & SYS0_SR_HRSTIN) >> 1) & 0x1)
#define SYS0_SR_HRSTIN_SET(reg,val) (reg) = ((reg & ~SYS0_SR_HRSTIN) | (((val) & 0x1) << 1))
/* Power-on Reset Indication (0) */
#define SYS0_SR_POR (0x1 << 0)
#define SYS0_SR_POR_VAL(val) (((val) & 0x1) << 0)
#define SYS0_SR_POR_GET(val) ((((val) & SYS0_SR_POR) >> 0) & 0x1)
#define SYS0_SR_POR_SET(reg,val) (reg) = ((reg & ~SYS0_SR_POR) | (((val) & 0x1) << 0))
/*******************************************************************************
* SYS0 Boot Control Register
******************************************************************************/
/* Configuration of Boot Source for CPU5 (25) */
#define SYS0_BCR_BMODECPU5 (0x1 << 25)
#define SYS0_BCR_BMODECPU5_VAL(val) (((val) & 0x1) << 25)
#define SYS0_BCR_BMODECPU5_GET(val) ((((val) & SYS0_BCR_BMODECPU5) >> 25) & 0x1)
#define SYS0_BCR_BMODECPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU5) | (((val) & 0x1) << 25))
/* Configuration of Boot Source for CPU4 (24) */
#define SYS0_BCR_BMODECPU4 (0x1 << 24)
#define SYS0_BCR_BMODECPU4_VAL(val) (((val) & 0x1) << 24)
#define SYS0_BCR_BMODECPU4_GET(val) ((((val) & SYS0_BCR_BMODECPU4) >> 24) & 0x1)
#define SYS0_BCR_BMODECPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU4) | (((val) & 0x1) << 24))
/* Configuration of Boot Source for CPU3 (23) */
#define SYS0_BCR_BMODECPU3 (0x1 << 23)
#define SYS0_BCR_BMODECPU3_VAL(val) (((val) & 0x1) << 23)
#define SYS0_BCR_BMODECPU3_GET(val) ((((val) & SYS0_BCR_BMODECPU3) >> 23) & 0x1)
#define SYS0_BCR_BMODECPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU3) | (((val) & 0x1) << 23))
/* Configuration of Boot Source for CPU2 (22) */
#define SYS0_BCR_BMODECPU2 (0x1 << 22)
#define SYS0_BCR_BMODECPU2_VAL(val) (((val) & 0x1) << 22)
#define SYS0_BCR_BMODECPU2_GET(val) ((((val) & SYS0_BCR_BMODECPU2) >> 22) & 0x1)
#define SYS0_BCR_BMODECPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU2) | (((val) & 0x1) << 22))
/* Configuration of Boot Source for CPU1 (21) */
#define SYS0_BCR_BMODECPU1 (0x1 << 21)
#define SYS0_BCR_BMODECPU1_VAL(val) (((val) & 0x1) << 21)
#define SYS0_BCR_BMODECPU1_GET(val) ((((val) & SYS0_BCR_BMODECPU1) >> 21) & 0x1)
#define SYS0_BCR_BMODECPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU1) | (((val) & 0x1) << 21))
/* Configuration of Boot Source for CPU0 (20:16) */
#define SYS0_BCR_BMODECPU0 (0x1f << 16)
#define SYS0_BCR_BMODECPU0_VAL(val) (((val) & 0x1f) << 16)
#define SYS0_BCR_BMODECPU0_GET(val) ((((val) & SYS0_BCR_BMODECPU0) >> 16) & 0x1f)
#define SYS0_BCR_BMODECPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU0) | (((val) & 0x1f) << 16))
/* Configuration of Endianess for CPU5 (5) */
#define SYS0_BCR_ESELCPU5 (0x1 << 5)
#define SYS0_BCR_ESELCPU5_VAL(val) (((val) & 0x1) << 5)
#define SYS0_BCR_ESELCPU5_GET(val) ((((val) & SYS0_BCR_ESELCPU5) >> 5) & 0x1)
#define SYS0_BCR_ESELCPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU5) | (((val) & 0x1) << 5))
/* Configuration of Endianess for CPU4 (4) */
#define SYS0_BCR_ESELCPU4 (0x1 << 4)
#define SYS0_BCR_ESELCPU4_VAL(val) (((val) & 0x1) << 4)
#define SYS0_BCR_ESELCPU4_GET(val) ((((val) & SYS0_BCR_ESELCPU4) >> 4) & 0x1)
#define SYS0_BCR_ESELCPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU4) | (((val) & 0x1) << 4))
/* Configuration of Endianess for CPU3 (3) */
#define SYS0_BCR_ESELCPU3 (0x1 << 3)
#define SYS0_BCR_ESELCPU3_VAL(val) (((val) & 0x1) << 3)
#define SYS0_BCR_ESELCPU3_GET(val) ((((val) & SYS0_BCR_ESELCPU3) >> 3) & 0x1)
#define SYS0_BCR_ESELCPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU3) | (((val) & 0x1) << 3))
/* Configuration of Endianess for CPU2 (2) */
#define SYS0_BCR_ESELCPU2 (0x1 << 2)
#define SYS0_BCR_ESELCPU2_VAL(val) (((val) & 0x1) << 2)
#define SYS0_BCR_ESELCPU2_GET(val) ((((val) & SYS0_BCR_ESELCPU2) >> 2) & 0x1)
#define SYS0_BCR_ESELCPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU2) | (((val) & 0x1) << 2))
/* Configuration of Endianess for CPU1 (1) */
#define SYS0_BCR_ESELCPU1 (0x1 << 1)
#define SYS0_BCR_ESELCPU1_VAL(val) (((val) & 0x1) << 1)
#define SYS0_BCR_ESELCPU1_GET(val) ((((val) & SYS0_BCR_ESELCPU1) >> 1) & 0x1)
#define SYS0_BCR_ESELCPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU1) | (((val) & 0x1) << 1))
/* Configuration of Endianess for CPU0 (0) */
#define SYS0_BCR_ESELCPU0 (0x1)
#define SYS0_BCR_ESELCPU0_VAL(val) (((val) & 0x1) << 0)
#define SYS0_BCR_ESELCPU0_GET(val) ((((val) & SYS0_BCR_ESELCPU0) >> 0) & 0x1)
#define SYS0_BCR_ESELCPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU0) | (((val) & 0x1) << 0))
/*******************************************************************************
* PLL1 Control Register
******************************************************************************/
/* PLL1 Bypass Enable (31) */
#define SYS0_PLL1CR_OSCBYP (0x1 << 31)
#define SYS0_PLL1CR_OSCBYP_VAL(val) (((val) & 0x1) << 31)
#define SYS0_PLL1CR_OSCBYP_GET(val) ((((val) & SYS0_PLL1CR_OSCBYP) >> 31) & 0x1)
#define SYS0_PLL1CR_OSCBYP_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_OSCBYP) | (((val) & 0x1) << 31))
/* PLL1 Divider Value (1:0) */
#define SYS0_PLL1CR_PLLDIV (0x3)
#define SYS0_PLL1CR_PLLDIV_VAL(val) (((val) & 0x3) << 0)
#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3)
#define SYS0_PLL1CR_PLLDIV_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_PLLDIV) | (((val) & 0x3) << 0))
/*******************************************************************************
* PLL2 Control Register
******************************************************************************/
/* PLL2 clear deepsleep (31) */
#define SYS0_PLL2CR_CLRDS (0x1 << 31)
#define SYS0_PLL2CR_CLRDS_VAL(val) (((val) & 0x1) << 31)
#define SYS0_PLL2CR_CLRDS_GET(val) ((((val) & SYS0_PLL2CR_CLRDS) >> 31) & 0x1)
#define SYS0_PLL2CR_CLRDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_CLRDS) | (((val) & 0x1) << 31))
/* PLL2 set deepsleep (30) */
#define SYS0_PLL2CR_SETDS (0x1 << 30)
#define SYS0_PLL2CR_SETDS_VAL(val) (((val) & 0x1) << 30)
#define SYS0_PLL2CR_SETDS_GET(val) ((((val) & SYS0_PLL2CR_SETDS) >> 30) & 0x1)
#define SYS0_PLL2CR_SETDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_SETDS) | (((val) & 0x1) << 30))
/* PLL2 Fractional division enable (16) */
#define SYS0_PLL2CR_FRACTEN (0x1 << 16)
#define SYS0_PLL2CR_FRACTEN_VAL(val) (((val) & 0x1) << 16)
#define SYS0_PLL2CR_FRACTEN_GET(val) ((((val) & SYS0_PLL2CR_FRACTEN) >> 16) & 0x1)
#define SYS0_PLL2CR_FRACTEN_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_FRACTEN) | (((val) & 0x1) << 16))
/* PLL2 Fractional division value (9:0) */
#define SYS0_FRACTVAL (0x3f)
#define SYS0_FRACTVAL_VAL(val) (((val) & 0x3f) << 0)
#define SYS0_FRACTVAL_GET(val) ((((val) & SYS0_FRACTVAL) >> 0) & 0x3f)
#define SYS0_FRACTVAL_SET(reg,val) (reg) = ((reg & ~SYS0_FRACTVAL) | (((val) & 0x3f) << 0))
#endif

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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __SYS1_REG_H
#define __SYS1_REG_H
#define sys1_r32(reg) ltq_r32(&sys1->reg)
#define sys1_w32(val, reg) ltq_w32(val, &sys1->reg)
#define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg)
/** SYS1 register structure */
struct svip_reg_sys1 {
unsigned long clksr; /* 0x0000 */
unsigned long clkenr; /* 0x0004 */
unsigned long clkclr; /* 0x0008 */
unsigned long reserved0[1];
unsigned long l2ccr; /* 0x0010 */
unsigned long fpicr; /* 0x0014 */
unsigned long wdtcr; /* 0x0018 */
unsigned long reserved1[1];
unsigned long cpucr[6]; /* 0x0020 */
unsigned long reserved2[2];
unsigned long rsr; /* 0x0040 */
unsigned long rreqr; /* 0x0044 */
unsigned long rrlsr; /* 0x0048 */
unsigned long rbtr; /* 0x004c */
unsigned long irncr; /* 0x0050 */
unsigned long irnicr; /* 0x0054 */
unsigned long irnen; /* 0x0058 */
unsigned long reserved3[1];
unsigned long cpursr[6]; /* 0x0060 */
unsigned long reserved4[2];
unsigned long cpusrssr[6]; /* 0x0080 */
unsigned long reserved5[2];
unsigned long cpuwrssr[6]; /* 0x00a0 */
};
/*******************************************************************************
* SYS1 Clock Status Register
******************************************************************************/
/* (r) Clock Enable for L2C */
#define SYS1_CLKSR_L2C (0x1 << 31)
/* (r) Clock Enable for DDR2 */
#define SYS1_CLKSR_DDR2 (0x1 << 30)
/* (r) Clock Enable for SMI2 */
#define SYS1_CLKSR_SMI2 (0x1 << 29)
/* (r) Clock Enable for SMI1 */
#define SYS1_CLKSR_SMI1 (0x1 << 28)
/* (r) Clock Enable for SMI0 */
#define SYS1_CLKSR_SMI0 (0x1 << 27)
/* (r) Clock Enable for FMI0 */
#define SYS1_CLKSR_FMI0 (0x1 << 26)
/* (r) Clock Enable for PORT0 */
#define SYS1_CLKSR_PORT0 (0x1 << 0)
/* (r) Clock Enable for PCM3 */
#define SYS1_CLKSR_PCM3 (0x1 << 19)
/* (r) Clock Enable for PCM2 */
#define SYS1_CLKSR_PCM2 (0x1 << 18)
/* (r) Clock Enable for PCM1 */
#define SYS1_CLKSR_PCM1 (0x1 << 17)
/* (r) Clock Enable for PCM0 */
#define SYS1_CLKSR_PCM0 (0x1 << 16)
/* (r) Clock Enable for ASC1 */
#define SYS1_CLKSR_ASC1 (0x1 << 15)
/* (r) Clock Enable for ASC0 */
#define SYS1_CLKSR_ASC0 (0x1 << 14)
/* (r) Clock Enable for SSC2 */
#define SYS1_CLKSR_SSC2 (0x1 << 13)
/* (r) Clock Enable for SSC1 */
#define SYS1_CLKSR_SSC1 (0x1 << 12)
/* (r) Clock Enable for SSC0 */
#define SYS1_CLKSR_SSC0 (0x1 << 11)
/* (r) Clock Enable for GPTC */
#define SYS1_CLKSR_GPTC (0x1 << 10)
/* (r) Clock Enable for DMA */
#define SYS1_CLKSR_DMA (0x1 << 9)
/* (r) Clock Enable for FSCT */
#define SYS1_CLKSR_FSCT (0x1 << 8)
/* (r) Clock Enable for ETHSW */
#define SYS1_CLKSR_ETHSW (0x1 << 7)
/* (r) Clock Enable for EBU */
#define SYS1_CLKSR_EBU (0x1 << 6)
/* (r) Clock Enable for TRNG */
#define SYS1_CLKSR_TRNG (0x1 << 5)
/* (r) Clock Enable for DEU */
#define SYS1_CLKSR_DEU (0x1 << 4)
/* (r) Clock Enable for PORT3 */
#define SYS1_CLKSR_PORT3 (0x1 << 3)
/* (r) Clock Enable for PORT2 */
#define SYS1_CLKSR_PORT2 (0x1 << 2)
/* (r) Clock Enable for PORT1 */
#define SYS1_CLKSR_PORT1 (0x1 << 1)
/*******************************************************************************
* SYS1 Clock Enable Register
******************************************************************************/
/* (w) Clock Enable Request for L2C */
#define SYS1_CLKENR_L2C (0x1 << 31)
/* (w) Clock Enable Request for DDR2 */
#define SYS1_CLKENR_DDR2 (0x1 << 30)
/* (w) Clock Enable Request for SMI2 */
#define SYS1_CLKENR_SMI2 (0x1 << 29)
/* (w) Clock Enable Request for SMI1 */
#define SYS1_CLKENR_SMI1 (0x1 << 28)
/* (w) Clock Enable Request for SMI0 */
#define SYS1_CLKENR_SMI0 (0x1 << 27)
/* (w) Clock Enable Request for FMI0 */
#define SYS1_CLKENR_FMI0 (0x1 << 26)
/* (w) Clock Enable Request for PORT0 */
#define SYS1_CLKENR_PORT0 (0x1 << 0)
/* (w) Clock Enable Request for PCM3 */
#define SYS1_CLKENR_PCM3 (0x1 << 19)
/* (w) Clock Enable Request for PCM2 */
#define SYS1_CLKENR_PCM2 (0x1 << 18)
/* (w) Clock Enable Request for PCM1 */
#define SYS1_CLKENR_PCM1 (0x1 << 17)
/* (w) Clock Enable Request for PCM0 */
#define SYS1_CLKENR_PCM0 (0x1 << 16)
/* (w) Clock Enable Request for ASC1 */
#define SYS1_CLKENR_ASC1 (0x1 << 15)
/* (w) Clock Enable Request for ASC0 */
#define SYS1_CLKENR_ASC0 (0x1 << 14)
/* (w) Clock Enable Request for SSC2 */
#define SYS1_CLKENR_SSC2 (0x1 << 13)
/* (w) Clock Enable Request for SSC1 */
#define SYS1_CLKENR_SSC1 (0x1 << 12)
/* (w) Clock Enable Request for SSC0 */
#define SYS1_CLKENR_SSC0 (0x1 << 11)
/* (w) Clock Enable Request for GPTC */
#define SYS1_CLKENR_GPTC (0x1 << 10)
/* (w) Clock Enable Request for DMA */
#define SYS1_CLKENR_DMA (0x1 << 9)
/* (w) Clock Enable Request for FSCT */
#define SYS1_CLKENR_FSCT (0x1 << 8)
/* (w) Clock Enable Request for ETHSW */
#define SYS1_CLKENR_ETHSW (0x1 << 7)
/* (w) Clock Enable Request for EBU */
#define SYS1_CLKENR_EBU (0x1 << 6)
/* (w) Clock Enable Request for TRNG */
#define SYS1_CLKENR_TRNG (0x1 << 5)
/* (w) Clock Enable Request for DEU */
#define SYS1_CLKENR_DEU (0x1 << 4)
/* (w) Clock Enable Request for PORT3 */
#define SYS1_CLKENR_PORT3 (0x1 << 3)
/* (w) Clock Enable Request for PORT2 */
#define SYS1_CLKENR_PORT2 (0x1 << 2)
/* (w) Clock Enable Request for PORT1 */
#define SYS1_CLKENR_PORT1 (0x1 << 1)
/*******************************************************************************
* SYS1 Clock Clear Register
******************************************************************************/
/* (w) Clock Disable Request for L2C */
#define SYS1_CLKCLR_L2C (0x1 << 31)
/* (w) Clock Disable Request for DDR2 */
#define SYS1_CLKCLR_DDR2 (0x1 << 30)
/* (w) Clock Disable Request for SMI2 */
#define SYS1_CLKCLR_SMI2 (0x1 << 29)
/* (w) Clock Disable Request for SMI1 */
#define SYS1_CLKCLR_SMI1 (0x1 << 28)
/* (w) Clock Disable Request for SMI0 */
#define SYS1_CLKCLR_SMI0 (0x1 << 27)
/* (w) Clock Disable Request for FMI0 */
#define SYS1_CLKCLR_FMI0 (0x1 << 26)
/* (w) Clock Disable Request for PORT0 */
#define SYS1_CLKCLR_PORT0 (0x1 << 0)
/* (w) Clock Disable Request for PCM3 */
#define SYS1_CLKCLR_PCM3 (0x1 << 19)
/* (w) Clock Disable Request for PCM2 */
#define SYS1_CLKCLR_PCM2 (0x1 << 18)
/* (w) Clock Disable Request for PCM1 */
#define SYS1_CLKCLR_PCM1 (0x1 << 17)
/* (w) Clock Disable Request for PCM0 */
#define SYS1_CLKCLR_PCM0 (0x1 << 16)
/* (w) Clock Disable Request for ASC1 */
#define SYS1_CLKCLR_ASC1 (0x1 << 15)
/* (w) Clock Disable Request for ASC0 */
#define SYS1_CLKCLR_ASC0 (0x1 << 14)
/* (w) Clock Disable Request for SSC2 */
#define SYS1_CLKCLR_SSC2 (0x1 << 13)
/* (w) Clock Disable Request for SSC1 */
#define SYS1_CLKCLR_SSC1 (0x1 << 12)
/* (w) Clock Disable Request for SSC0 */
#define SYS1_CLKCLR_SSC0 (0x1 << 11)
/* (w) Clock Disable Request for GPTC */
#define SYS1_CLKCLR_GPTC (0x1 << 10)
/* (w) Clock Disable Request for DMA */
#define SYS1_CLKCLR_DMA (0x1 << 9)
/* (w) Clock Disable Request for FSCT */
#define SYS1_CLKCLR_FSCT (0x1 << 8)
/* (w) Clock Disable Request for ETHSW */
#define SYS1_CLKCLR_ETHSW (0x1 << 7)
/* (w) Clock Disable Request for EBU */
#define SYS1_CLKCLR_EBU (0x1 << 6)
/* (w) Clock Disable Request for TRNG */
#define SYS1_CLKCLR_TRNG (0x1 << 5)
/* (w) Clock Disable Request for DEU */
#define SYS1_CLKCLR_DEU (0x1 << 4)
/* (w) Clock Disable Request for PORT3 */
#define SYS1_CLKCLR_PORT3 (0x1 << 3)
/* (w) Clock Disable Request for PORT2 */
#define SYS1_CLKCLR_PORT2 (0x1 << 2)
/* (w) Clock Disable Request for PORT1 */
#define SYS1_CLKCLR_PORT1 (0x1 << 1)
/*******************************************************************************
* SYS1 FPI Control Register
******************************************************************************/
/* FPI Bus Clock divider (0) */
#define SYS1_FPICR_FPIDIV (0x1)
#define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0)
#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1)
#define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0))
/*******************************************************************************
* SYS1 Clock Control Register for CPUn
******************************************************************************/
/* Enable bit for clock of CPUn (1) */
#define SYS1_CPUCR_CPUCLKEN (0x1 << 1)
#define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1)
#define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1)
#define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1))
/* Divider factor for clock of CPUn (0) */
#define SYS1_CPUCR_CPUDIV (0x1)
#define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0)
#define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1)
#define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0))
/*******************************************************************************
* SYS1 Reset Request Register
******************************************************************************/
/* HRSTOUT Reset Request (18) */
#define SYS1_RREQ_HRSTOUT (0x1 << 18)
#define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18)
#define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18))
/* FBS0 Reset Request (17) */
#define SYS1_RREQ_FBS0 (0x1 << 17)
#define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17)
#define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17))
/* SUBSYS Reset Request (16) */
#define SYS1_RREQ_SUBSYS (0x1 << 16)
#define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16)
#define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16))
/* Watchdog5 Reset Request (13) */
#define SYS1_RREQ_WDT5 (0x1 << 13)
#define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13)
#define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13))
/* Watchdog4 Reset Request (12) */
#define SYS1_RREQ_WDT4 (0x1 << 12)
#define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12)
#define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12))
/* Watchdog3 Reset Request (11) */
#define SYS1_RREQ_WDT3 (0x1 << 11)
#define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11)
#define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11))
/* Watchdog2 Reset Request (10) */
#define SYS1_RREQ_WDT2 (0x1 << 10)
#define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10)
#define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10))
/* Watchdog1 Reset Request (9) */
#define SYS1_RREQ_WDT1 (0x1 << 9)
#define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9)
#define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9))
/* Watchdog0 Reset Request (8) */
#define SYS1_RREQ_WDT0 (0x1 << 8)
#define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8)
#define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8))
/* CPU5 Reset Request (5) */
#define SYS1_RREQ_CPU5 (0x1 << 5)
#define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5)
#define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5))
/* CPU4 Reset Request (4) */
#define SYS1_RREQ_CPU4 (0x1 << 4)
#define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4)
#define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4))
/* CPU3 Reset Request (3) */
#define SYS1_RREQ_CPU3 (0x1 << 3)
#define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3)
#define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3))
/* CPU2 Reset Request (2) */
#define SYS1_RREQ_CPU2 (0x1 << 2)
#define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2)
#define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2))
/* CPU1 Reset Request (1) */
#define SYS1_RREQ_CPU1 (0x1 << 1)
#define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1)
#define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1))
/* CPU0 Reset Request (0) */
#define SYS1_RREQ_CPU0 (0x1)
#define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0)
#define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0))
/*******************************************************************************
* SYS1 Reset Release Register
******************************************************************************/
/* HRSTOUT Reset Release (18) */
#define SYS1_RRLSR_HRSTOUT (0x1 << 18)
#define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18)
#define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18))
/* FBS0 Reset Release (17) */
#define SYS1_RRLSR_FBS0 (0x1 << 17)
#define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17)
#define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17))
/* SUBSYS Reset Release (16) */
#define SYS1_RRLSR_SUBSYS (0x1 << 16)
#define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16)
#define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16))
/* Watchdog5 Reset Release (13) */
#define SYS1_RRLSR_WDT5 (0x1 << 13)
#define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13)
#define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13))
/* Watchdog4 Reset Release (12) */
#define SYS1_RRLSR_WDT4 (0x1 << 12)
#define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12)
#define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12))
/* Watchdog3 Reset Release (11) */
#define SYS1_RRLSR_WDT3 (0x1 << 11)
#define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11)
#define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11))
/* Watchdog2 Reset Release (10) */
#define SYS1_RRLSR_WDT2 (0x1 << 10)
#define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10)
#define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10))
/* Watchdog1 Reset Release (9) */
#define SYS1_RRLSR_WDT1 (0x1 << 9)
#define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9)
#define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9))
/* Watchdog0 Reset Release (8) */
#define SYS1_RRLSR_WDT0 (0x1 << 8)
#define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8)
#define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8))
/* CPU5 Reset Release (5) */
#define SYS1_RRLSR_CPU5 (0x1 << 5)
#define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5)
#define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5))
/* CPU4 Reset Release (4) */
#define SYS1_RRLSR_CPU4 (0x1 << 4)
#define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4)
#define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4))
/* CPU3 Reset Release (3) */
#define SYS1_RRLSR_CPU3 (0x1 << 3)
#define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3)
#define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3))
/* CPU2 Reset Release (2) */
#define SYS1_RRLSR_CPU2 (0x1 << 2)
#define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2)
#define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2))
/* CPU1 Reset Release (1) */
#define SYS1_RRLSR_CPU1 (0x1 << 1)
#define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1)
#define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1))
/* CPU0 Reset Release (0) */
#define SYS1_RRLSR_CPU0 (0x1)
#define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0)
#define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0))
#endif

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target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h Normal file
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/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __SYS2_REG_H
#define __SYS2_REG_H
#define sys2_r32(reg) ltq_r32(&sys2->reg)
#define sys2_w32(val, reg) ltq_w32(val, &sys2->reg)
#define sys2_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys2->reg)
/** SYS2 register structure */
struct svip_reg_sys2 {
volatile unsigned long clksr; /* 0x0000 */
volatile unsigned long clkenr; /* 0x0004 */
volatile unsigned long clkclr; /* 0x0008 */
volatile unsigned long reserved0[1];
volatile unsigned long rsr; /* 0x0010 */
volatile unsigned long rreqr; /* 0x0014 */
volatile unsigned long rrlsr; /* 0x0018 */
};
/*******************************************************************************
* SYS2 Clock Status Register
******************************************************************************/
/* Clock Enable for PORT4 */
#define SYS2_CLKSR_PORT4 (0x1 << 27)
#define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27)
#define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27)
/* Clock Enable for HWSYNC */
#define SYS2_CLKSR_HWSYNC (0x1 << 26)
#define SYS2_CLKSR_HWSYNC_VAL(val) (((val) &
#define SYS2_CLKSR_HWSYNC_GET(val) (((val) & SYS2_CLKSR_HWSYNC) >> 26)
/* Clock Enable for MBS */
#define SYS2_CLKSR_MBS (0x1 << 25)
#define SYS2_CLKSR_MBS_VAL(val) (((val) & 0x1) << 25)
#define SYS2_CLKSR_MBS_GET(val) (((val) & SYS2_CLKSR_MBS) >> 25)
/* Clock Enable for SWINT */
#define SYS2_CLKSR_SWINT (0x1 << 24)
#define SYS2_CLKSR_SWINT_VAL(val) (((val) & 0x1) << 24)
#define SYS2_CLKSR_SWINT_GET(val) (((val) & SYS2_CLKSR_SWINT) >> 24)
/* Clock Enable for HWACC3 */
#define SYS2_CLKSR_HWACC3 (0x1 << 19)
#define SYS2_CLKSR_HWACC3_VAL(val) (((val) &
#define SYS2_CLKSR_HWACC3_GET(val) (((val) & SYS2_CLKSR_HWACC3) >> 19)
/* Clock Enable for HWACC2 */
#define SYS2_CLKSR_HWACC2 (0x1 << 18)
#define SYS2_CLKSR_HWACC2_VAL(val) (((val) &
#define SYS2_CLKSR_HWACC2_GET(val) (((val) & SYS2_CLKSR_HWACC2) >> 18)
/* Clock Enable for HWACC1 */
#define SYS2_CLKSR_HWACC1 (0x1 << 17)
#define SYS2_CLKSR_HWACC1_VAL(val) (((val) &
#define SYS2_CLKSR_HWACC1_GET(val) (((val) & SYS2_CLKSR_HWACC1) >> 17)
/* Clock Enable for HWACC0 */
#define SYS2_CLKSR_HWACC0 (0x1 << 16)
#define SYS2_CLKSR_HWACC0_VAL(val) (((val) &
#define SYS2_CLKSR_HWACC0_GET(val) (((val) & SYS2_CLKSR_HWACC0) >> 16)
/* Clock Enable for SIF7 */
#define SYS2_CLKSR_SIF7 (0x1 << 15)
#define SYS2_CLKSR_SIF7_VAL(val) (((val) & 0x1) << 15)
#define SYS2_CLKSR_SIF7_GET(val) (((val) & SYS2_CLKSR_SIF7) >> 15)
/* Clock Enable for SIF6 */
#define SYS2_CLKSR_SIF6 (0x1 << 14)
#define SYS2_CLKSR_SIF6_VAL(val) (((val) & 0x1) << 14)
#define SYS2_CLKSR_SIF6_GET(val) (((val) & SYS2_CLKSR_SIF6) >> 14)
/* Clock Enable for SIF5 */
#define SYS2_CLKSR_SIF5 (0x1 << 13)
#define SYS2_CLKSR_SIF5_VAL(val) (((val) & 0x1) << 13)
#define SYS2_CLKSR_SIF5_GET(val) (((val) & SYS2_CLKSR_SIF5) >> 13)
/* Clock Enable for SIF4 */
#define SYS2_CLKSR_SIF4 (0x1 << 12)
#define SYS2_CLKSR_SIF4_VAL(val) (((val) & 0x1) << 12)
#define SYS2_CLKSR_SIF4_GET(val) (((val) & SYS2_CLKSR_SIF4) >> 12)
/* Clock Enable for SIF3 */
#define SYS2_CLKSR_SIF3 (0x1 << 11)
#define SYS2_CLKSR_SIF3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_CLKSR_SIF3_GET(val) (((val) & SYS2_CLKSR_SIF3) >> 11)
/* Clock Enable for SIF2 */
#define SYS2_CLKSR_SIF2 (0x1 << 10)
#define SYS2_CLKSR_SIF2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_CLKSR_SIF2_GET(val) (((val) & SYS2_CLKSR_SIF2) >> 10)
/* Clock Enable for SIF1 */
#define SYS2_CLKSR_SIF1 (0x1 << 9)
#define SYS2_CLKSR_SIF1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_CLKSR_SIF1_GET(val) (((val) & SYS2_CLKSR_SIF1) >> 9)
/* Clock Enable for SIF0 */
#define SYS2_CLKSR_SIF0 (0x1 << 8)
#define SYS2_CLKSR_SIF0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_CLKSR_SIF0_GET(val) (((val) & SYS2_CLKSR_SIF0) >> 8)
/* Clock Enable for DFEV7 */
#define SYS2_CLKSR_DFEV7 (0x1 << 7)
#define SYS2_CLKSR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_CLKSR_DFEV7_GET(val) (((val) & SYS2_CLKSR_DFEV7) >> 7)
/* Clock Enable for DFEV6 */
#define SYS2_CLKSR_DFEV6 (0x1 << 6)
#define SYS2_CLKSR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_CLKSR_DFEV6_GET(val) (((val) & SYS2_CLKSR_DFEV6) >> 6)
/* Clock Enable for DFEV5 */
#define SYS2_CLKSR_DFEV5 (0x1 << 5)
#define SYS2_CLKSR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_CLKSR_DFEV5_GET(val) (((val) & SYS2_CLKSR_DFEV5) >> 5)
/* Clock Enable for DFEV4 */
#define SYS2_CLKSR_DFEV4 (0x1 << 4)
#define SYS2_CLKSR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_CLKSR_DFEV4_GET(val) (((val) & SYS2_CLKSR_DFEV4) >> 4)
/* Clock Enable for DFEV3 */
#define SYS2_CLKSR_DFEV3 (0x1 << 3)
#define SYS2_CLKSR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_CLKSR_DFEV3_GET(val) (((val) & SYS2_CLKSR_DFEV3) >> 3)
/* Clock Enable for DFEV2 */
#define SYS2_CLKSR_DFEV2 (0x1 << 2)
#define SYS2_CLKSR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_CLKSR_DFEV2_GET(val) (((val) & SYS2_CLKSR_DFEV2) >> 2)
/* Clock Enable for DFEV1 */
#define SYS2_CLKSR_DFEV1 (0x1 << 1)
#define SYS2_CLKSR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_CLKSR_DFEV1_GET(val) (((val) & SYS2_CLKSR_DFEV1) >> 1)
/* Clock Enable for DFEV0 */
#define SYS2_CLKSR_DFEV0 (0x1)
#define SYS2_CLKSR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_CLKSR_DFEV0_GET(val) ((val) & SYS2_CLKSR_DFEV0)
/*******************************************************************************
* SYS2 Clock Enable Register
******************************************************************************/
/* Clock Enable Request for PORT4 */
#define SYS2_CLKENR_PORT4 (0x1 << 27)
#define SYS2_CLKENR_PORT4_VAL(val) (((val) & 0x1) << 27)
#define SYS2_CLKENR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_PORT4) | ((val & 0x1) << 27))
/* Clock Enable Request for HWSYNC */
#define SYS2_CLKENR_HWSYNC (0x1 << 26)
#define SYS2_CLKENR_HWSYNC_VAL(val) (((val) & 0x1) << 26)
#define SYS2_CLKENR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWSYNC) | ((val & 0x1) << 26))
/* Clock Enable Request for MBS */
#define SYS2_CLKENR_MBS (0x1 << 25)
#define SYS2_CLKENR_MBS_VAL(val) (((val) & 0x1) << 25)
#define SYS2_CLKENR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_MBS) | ((val & 0x1) << 25))
/* Clock Enable Request for SWINT */
#define SYS2_CLKENR_SWINT (0x1 << 24)
#define SYS2_CLKENR_SWINT_VAL(val) (((val) & 0x1) << 24)
#define SYS2_CLKENR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SWINT) | ((val & 0x1) << 24))
/* Clock Enable Request for HWACC3 */
#define SYS2_CLKENR_HWACC3 (0x1 << 19)
#define SYS2_CLKENR_HWACC3_VAL(val) (((val) & 0x1) << 19)
#define SYS2_CLKENR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC3) | ((val & 0x1) << 19))
/* Clock Enable Request for HWACC2 */
#define SYS2_CLKENR_HWACC2 (0x1 << 18)
#define SYS2_CLKENR_HWACC2_VAL(val) (((val) & 0x1) << 18)
#define SYS2_CLKENR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC2) | ((val & 0x1) << 18))
/* Clock Enable Request for HWACC1 */
#define SYS2_CLKENR_HWACC1 (0x1 << 17)
#define SYS2_CLKENR_HWACC1_VAL(val) (((val) & 0x1) << 17)
#define SYS2_CLKENR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC1) | ((val & 0x1) << 17))
/* Clock Enable Request for HWACC0 */
#define SYS2_CLKENR_HWACC0 (0x1 << 16)
#define SYS2_CLKENR_HWACC0_VAL(val) (((val) & 0x1) << 16)
#define SYS2_CLKENR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC0) | ((val & 0x1) << 16))
/* Clock Enable Request for SIF7 */
#define SYS2_CLKENR_SIF7 (0x1 << 15)
#define SYS2_CLKENR_SIF7_VAL(val) (((val) & 0x1) << 15)
#define SYS2_CLKENR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF7) | ((val & 0x1) << 15))
/* Clock Enable Request for SIF6 */
#define SYS2_CLKENR_SIF6 (0x1 << 14)
#define SYS2_CLKENR_SIF6_VAL(val) (((val) & 0x1) << 14)
#define SYS2_CLKENR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF6) | ((val & 0x1) << 14))
/* Clock Enable Request for SIF5 */
#define SYS2_CLKENR_SIF5 (0x1 << 13)
#define SYS2_CLKENR_SIF5_VAL(val) (((val) & 0x1) << 13)
#define SYS2_CLKENR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF5) | ((val & 0x1) << 13))
/* Clock Enable Request for SIF4 */
#define SYS2_CLKENR_SIF4 (0x1 << 12)
#define SYS2_CLKENR_SIF4_VAL(val) (((val) & 0x1) << 12)
#define SYS2_CLKENR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF4) | ((val & 0x1) << 12))
/* Clock Enable Request for SIF3 */
#define SYS2_CLKENR_SIF3 (0x1 << 11)
#define SYS2_CLKENR_SIF3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_CLKENR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF3) | ((val & 0x1) << 11))
/* Clock Enable Request for SIF2 */
#define SYS2_CLKENR_SIF2 (0x1 << 10)
#define SYS2_CLKENR_SIF2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_CLKENR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF2) | ((val & 0x1) << 10))
/* Clock Enable Request for SIF1 */
#define SYS2_CLKENR_SIF1 (0x1 << 9)
#define SYS2_CLKENR_SIF1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_CLKENR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF1) | ((val & 0x1) << 9))
/* Clock Enable Request for SIF0 */
#define SYS2_CLKENR_SIF0 (0x1 << 8)
#define SYS2_CLKENR_SIF0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_CLKENR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF0) | ((val & 0x1) << 8))
/* Clock Enable Request for DFEV7 */
#define SYS2_CLKENR_DFEV7 (0x1 << 7)
#define SYS2_CLKENR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_CLKENR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV7) | ((val & 0x1) << 7))
/* Clock Enable Request for DFEV6 */
#define SYS2_CLKENR_DFEV6 (0x1 << 6)
#define SYS2_CLKENR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_CLKENR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV6) | ((val & 0x1) << 6))
/* Clock Enable Request for DFEV5 */
#define SYS2_CLKENR_DFEV5 (0x1 << 5)
#define SYS2_CLKENR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_CLKENR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV5) | ((val & 0x1) << 5))
/* Clock Enable Request for DFEV4 */
#define SYS2_CLKENR_DFEV4 (0x1 << 4)
#define SYS2_CLKENR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_CLKENR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV4) | ((val & 0x1) << 4))
/* Clock Enable Request for DFEV3 */
#define SYS2_CLKENR_DFEV3 (0x1 << 3)
#define SYS2_CLKENR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_CLKENR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV3) | ((val & 0x1) << 3))
/* Clock Enable Request for DFEV2 */
#define SYS2_CLKENR_DFEV2 (0x1 << 2)
#define SYS2_CLKENR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_CLKENR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV2) | ((val & 0x1) << 2))
/* Clock Enable Request for DFEV1 */
#define SYS2_CLKENR_DFEV1 (0x1 << 1)
#define SYS2_CLKENR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_CLKENR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV1) | ((val & 0x1) << 1))
/* Clock Enable Request for DFEV0 */
#define SYS2_CLKENR_DFEV0 (0x1)
#define SYS2_CLKENR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_CLKENR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV0) | ((val & 0x1)))
/*******************************************************************************
* SYS2 Clock Clear Register
******************************************************************************/
/* Clock Disable Request for PORT4 */
#define SYS2_CLKCLR_PORT4 (0x1 << 27)
#define SYS2_CLKCLR_PORT4_VAL(val) (((val) & 0x1) << 27)
#define SYS2_CLKCLR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_PORT4) | ((val & 0x1) << 27))
/* Clock Disable Request for HWSYNC */
#define SYS2_CLKCLR_HWSYNC (0x1 << 26)
#define SYS2_CLKCLR_HWSYNC_VAL(val) (((val) & 0x1) << 26)
#define SYS2_CLKCLR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWSYNC) | ((val & 0x1) << 26))
/* Clock Disable Request for MBS */
#define SYS2_CLKCLR_MBS (0x1 << 25)
#define SYS2_CLKCLR_MBS_VAL(val) (((val) & 0x1) << 25)
#define SYS2_CLKCLR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_MBS) | ((val & 0x1) << 25))
/* Clock Disable Request for SWINT */
#define SYS2_CLKCLR_SWINT (0x1 << 24)
#define SYS2_CLKCLR_SWINT_VAL(val) (((val) & 0x1) << 24)
#define SYS2_CLKCLR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SWINT) | ((val & 0x1) << 24))
/* Clock Disable Request for HWACC3 */
#define SYS2_CLKCLR_HWACC3 (0x1 << 19)
#define SYS2_CLKCLR_HWACC3_VAL(val) (((val) & 0x1) << 19)
#define SYS2_CLKCLR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC3) | ((val & 0x1) << 19))
/* Clock Disable Request for HWACC2 */
#define SYS2_CLKCLR_HWACC2 (0x1 << 18)
#define SYS2_CLKCLR_HWACC2_VAL(val) (((val) & 0x1) << 18)
#define SYS2_CLKCLR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC2) | ((val & 0x1) << 18))
/* Clock Disable Request for HWACC1 */
#define SYS2_CLKCLR_HWACC1 (0x1 << 17)
#define SYS2_CLKCLR_HWACC1_VAL(val) (((val) & 0x1) << 17)
#define SYS2_CLKCLR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC1) | ((val & 0x1) << 17))
/* Clock Disable Request for HWACC0 */
#define SYS2_CLKCLR_HWACC0 (0x1 << 16)
#define SYS2_CLKCLR_HWACC0_VAL(val) (((val) & 0x1) << 16)
#define SYS2_CLKCLR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC0) | ((val & 0x1) << 16))
/* Clock Disable Request for SIF7 */
#define SYS2_CLKCLR_SIF7 (0x1 << 15)
#define SYS2_CLKCLR_SIF7_VAL(val) (((val) & 0x1) << 15)
#define SYS2_CLKCLR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF7) | ((val & 0x1) << 15))
/* Clock Disable Request for SIF6 */
#define SYS2_CLKCLR_SIF6 (0x1 << 14)
#define SYS2_CLKCLR_SIF6_VAL(val) (((val) & 0x1) << 14)
#define SYS2_CLKCLR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF6) | ((val & 0x1) << 14))
/* Clock Disable Request for SIF5 */
#define SYS2_CLKCLR_SIF5 (0x1 << 13)
#define SYS2_CLKCLR_SIF5_VAL(val) (((val) & 0x1) << 13)
#define SYS2_CLKCLR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF5) | ((val & 0x1) << 13))
/* Clock Disable Request for SIF4 */
#define SYS2_CLKCLR_SIF4 (0x1 << 12)
#define SYS2_CLKCLR_SIF4_VAL(val) (((val) & 0x1) << 12)
#define SYS2_CLKCLR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF4) | ((val & 0x1) << 12))
/* Clock Disable Request for SIF3 */
#define SYS2_CLKCLR_SIF3 (0x1 << 11)
#define SYS2_CLKCLR_SIF3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_CLKCLR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF3) | ((val & 0x1) << 11))
/* Clock Disable Request for SIF2 */
#define SYS2_CLKCLR_SIF2 (0x1 << 10)
#define SYS2_CLKCLR_SIF2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_CLKCLR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF2) | ((val & 0x1) << 10))
/* Clock Disable Request for SIF1 */
#define SYS2_CLKCLR_SIF1 (0x1 << 9)
#define SYS2_CLKCLR_SIF1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_CLKCLR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF1) | ((val & 0x1) << 9))
/* Clock Disable Request for SIF0 */
#define SYS2_CLKCLR_SIF0 (0x1 << 8)
#define SYS2_CLKCLR_SIF0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_CLKCLR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF0) | ((val & 0x1) << 8))
/* Clock Disable Request for DFEV7 */
#define SYS2_CLKCLR_DFEV7 (0x1 << 7)
#define SYS2_CLKCLR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_CLKCLR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV7) | ((val & 0x1) << 7))
/* Clock Disable Request for DFEV6 */
#define SYS2_CLKCLR_DFEV6 (0x1 << 6)
#define SYS2_CLKCLR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_CLKCLR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV6) | ((val & 0x1) << 6))
/* Clock Disable Request for DFEV5 */
#define SYS2_CLKCLR_DFEV5 (0x1 << 5)
#define SYS2_CLKCLR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_CLKCLR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV5) | ((val & 0x1) << 5))
/* Clock Disable Request for DFEV4 */
#define SYS2_CLKCLR_DFEV4 (0x1 << 4)
#define SYS2_CLKCLR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_CLKCLR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV4) | ((val & 0x1) << 4))
/* Clock Disable Request for DFEV3 */
#define SYS2_CLKCLR_DFEV3 (0x1 << 3)
#define SYS2_CLKCLR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_CLKCLR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV3) | ((val & 0x1) << 3))
/* Clock Disable Request for DFEV2 */
#define SYS2_CLKCLR_DFEV2 (0x1 << 2)
#define SYS2_CLKCLR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_CLKCLR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV2) | ((val & 0x1) << 2))
/* Clock Disable Request for DFEV1 */
#define SYS2_CLKCLR_DFEV1 (0x1 << 1)
#define SYS2_CLKCLR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_CLKCLR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV1) | ((val & 0x1) << 1))
/* Clock Disable Request for DFEV0 */
#define SYS2_CLKCLR_DFEV0 (0x1)
#define SYS2_CLKCLR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_CLKCLR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV0) | ((val & 0x1)))
/*******************************************************************************
* SYS2 Reset Status Register
******************************************************************************/
/* HWACC3 Reset */
#define SYS2_RSR_HWACC3 (0x1 << 11)
#define SYS2_RSR_HWACC3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_RSR_HWACC3_GET(val) (((val) & SYS2_RSR_HWACC3) >> 11)
/* HWACC2 Reset */
#define SYS2_RSR_HWACC2 (0x1 << 10)
#define SYS2_RSR_HWACC2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_RSR_HWACC2_GET(val) (((val) & SYS2_RSR_HWACC2) >> 10)
/* HWACC1 Reset */
#define SYS2_RSR_HWACC1 (0x1 << 9)
#define SYS2_RSR_HWACC1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_RSR_HWACC1_GET(val) (((val) & SYS2_RSR_HWACC1) >> 9)
/* HWACC0 Reset */
#define SYS2_RSR_HWACC0 (0x1 << 8)
#define SYS2_RSR_HWACC0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_RSR_HWACC0_GET(val) (((val) & SYS2_RSR_HWACC0) >> 8)
/* DFEV7 Reset */
#define SYS2_RSR_DFEV7 (0x1 << 7)
#define SYS2_RSR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_RSR_DFEV7_GET(val) (((val) & SYS2_RSR_DFEV7) >> 7)
/* DFEV6 Reset */
#define SYS2_RSR_DFEV6 (0x1 << 6)
#define SYS2_RSR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_RSR_DFEV6_GET(val) (((val) & SYS2_RSR_DFEV6) >> 6)
/* DFEV5 Reset */
#define SYS2_RSR_DFEV5 (0x1 << 5)
#define SYS2_RSR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_RSR_DFEV5_GET(val) (((val) & SYS2_RSR_DFEV5) >> 5)
/* DFEV4 Reset */
#define SYS2_RSR_DFEV4 (0x1 << 4)
#define SYS2_RSR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_RSR_DFEV4_GET(val) (((val) & SYS2_RSR_DFEV4) >> 4)
/* DFEV3 Reset */
#define SYS2_RSR_DFEV3 (0x1 << 3)
#define SYS2_RSR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_RSR_DFEV3_GET(val) (((val) & SYS2_RSR_DFEV3) >> 3)
/* DFEV2 Reset */
#define SYS2_RSR_DFEV2 (0x1 << 2)
#define SYS2_RSR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_RSR_DFEV2_GET(val) (((val) & SYS2_RSR_DFEV2) >> 2)
/* DFEV1 Reset */
#define SYS2_RSR_DFEV1 (0x1 << 1)
#define SYS2_RSR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_RSR_DFEV1_GET(val) (((val) & SYS2_RSR_DFEV1) >> 1)
/* DFEV0 Reset */
#define SYS2_RSR_DFEV0 (0x1)
#define SYS2_RSR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_RSR_DFEV0_GET(val) ((val) & SYS2_RSR_DFEV0)
/******************************************************************************
* SYS2 Reset Request Register
******************************************************************************/
/* HWACC3 Reset Request */
#define SYS2_RREQR_HWACC3 (0x1 << 11)
#define SYS2_RREQR_HWACC3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_RREQR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC3) | ((val & 0x1) << 11))
/* HWACC2 Reset Request */
#define SYS2_RREQR_HWACC2 (0x1 << 10)
#define SYS2_RREQR_HWACC2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_RREQR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC2) | ((val & 0x1) << 10))
/* HWACC1 Reset Request */
#define SYS2_RREQR_HWACC1 (0x1 << 9)
#define SYS2_RREQR_HWACC1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_RREQR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC1) | ((val & 0x1) << 9))
/* HWACC0 Reset Request */
#define SYS2_RREQR_HWACC0 (0x1 << 8)
#define SYS2_RREQR_HWACC0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_RREQR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC0) | ((val & 0x1) << 8))
/* DFEV7 Reset Request */
#define SYS2_RREQR_DFEV7 (0x1 << 7)
#define SYS2_RREQR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_RREQR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV7) | ((val & 0x1) << 7))
/* DFEV6 Reset Request */
#define SYS2_RREQR_DFEV6 (0x1 << 6)
#define SYS2_RREQR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_RREQR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV6) | ((val & 0x1) << 6))
/* DFEV5 Reset Request */
#define SYS2_RREQR_DFEV5 (0x1 << 5)
#define SYS2_RREQR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_RREQR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV5) | ((val & 0x1) << 5))
/* DFEV4 Reset Request */
#define SYS2_RREQR_DFEV4 (0x1 << 4)
#define SYS2_RREQR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_RREQR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV4) | ((val & 0x1) << 4))
/* DFEV3 Reset Request */
#define SYS2_RREQR_DFEV3 (0x1 << 3)
#define SYS2_RREQR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_RREQR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV3) | ((val & 0x1) << 3))
/* DFEV2 Reset Request */
#define SYS2_RREQR_DFEV2 (0x1 << 2)
#define SYS2_RREQR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_RREQR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV2) | ((val & 0x1) << 2))
/* DFEV1 Reset Request */
#define SYS2_RREQR_DFEV1 (0x1 << 1)
#define SYS2_RREQR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_RREQR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV1) | ((val & 0x1) << 1))
/* DFEV0 Reset Request */
#define SYS2_RREQR_DFEV0 (0x1)
#define SYS2_RREQR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_RREQR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV0) | ((val & 0x1)))
/*******************************************************************************
* SYS2 Reset Release Register
******************************************************************************/
/* HWACC3 Reset Release */
#define SYS2_RRLSR_HWACC3 (0x1 << 11)
#define SYS2_RRLSR_HWACC3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_RRLSR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC3) | ((val & 0x1) << 11))
/* HWACC2 Reset Release */
#define SYS2_RRLSR_HWACC2 (0x1 << 10)
#define SYS2_RRLSR_HWACC2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_RRLSR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC2) | ((val & 0x1) << 10))
/* HWACC1 Reset Release */
#define SYS2_RRLSR_HWACC1 (0x1 << 9)
#define SYS2_RRLSR_HWACC1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_RRLSR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC1) | ((val & 0x1) << 9))
/* HWACC0 Reset Release */
#define SYS2_RRLSR_HWACC0 (0x1 << 8)
#define SYS2_RRLSR_HWACC0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_RRLSR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC0) | ((val & 0x1) << 8))
/* DFEV7 Reset Release */
#define SYS2_RRLSR_DFEV7 (0x1 << 7)
#define SYS2_RRLSR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_RRLSR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV7) | ((val & 0x1) << 7))
/* DFEV6 Reset Release */
#define SYS2_RRLSR_DFEV6 (0x1 << 6)
#define SYS2_RRLSR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_RRLSR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV6) | ((val & 0x1) << 6))
/* DFEV5 Reset Release */
#define SYS2_RRLSR_DFEV5 (0x1 << 5)
#define SYS2_RRLSR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_RRLSR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV5) | ((val & 0x1) << 5))
/* DFEV4 Reset Release */
#define SYS2_RRLSR_DFEV4 (0x1 << 4)
#define SYS2_RRLSR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_RRLSR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV4) | ((val & 0x1) << 4))
/* DFEV3 Reset Release */
#define SYS2_RRLSR_DFEV3 (0x1 << 3)
#define SYS2_RRLSR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_RRLSR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV3) | ((val & 0x1) << 3))
/* DFEV2 Reset Release */
#define SYS2_RRLSR_DFEV2 (0x1 << 2)
#define SYS2_RRLSR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_RRLSR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV2) | ((val & 0x1) << 2))
/* DFEV1 Reset Release */
#define SYS2_RRLSR_DFEV1 (0x1 << 1)
#define SYS2_RRLSR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_RRLSR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV1) | ((val & 0x1) << 1))
/* DFEV0 Reset Release */
#define SYS2_RRLSR_DFEV0 (0x1)
#define SYS2_RRLSR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_RRLSR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV0) | ((val & 0x1)))
#endif /* __SYS2_H */

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target/linux/lantiq/files/arch/mips/lantiq/falcon/Kconfig Normal file
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if SOC_FALCON
menu "MIPS Machine"
config LANTIQ_MACH_EASY98000
bool "Easy98000"
default y
endmenu
endif

2
target/linux/lantiq/files/arch/mips/lantiq/falcon/Makefile Normal file
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obj-y := prom.o reset.o sysctrl.o devices.o gpio.o
obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o

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target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#include <linux/platform_device.h>
#include <linux/mtd/nand.h>
#include <linux/gpio.h>
#include <lantiq_soc.h>
#include "devices.h"
/* nand flash */
/* address lines used for NAND control signals */
#define NAND_ADDR_ALE 0x10000
#define NAND_ADDR_CLE 0x20000
/* Ready/Busy Status */
#define MODCON_STS 0x0002
/* Ready/Busy Status Edge */
#define MODCON_STSEDGE 0x0004
static const char *part_probes[] = { "cmdlinepart", NULL };
static int
falcon_nand_ready(struct mtd_info *mtd)
{
u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
(MODCON_STS | MODCON_STSEDGE)));
}
static void
falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
if (ctrl & NAND_CLE)
nandaddr |= NAND_ADDR_CLE;
if (ctrl & NAND_ALE)
nandaddr |= NAND_ADDR_ALE;
this->IO_ADDR_W = (void __iomem *) nandaddr;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static struct platform_nand_data falcon_flash_nand_data = {
.chip = {
.nr_chips = 1,
.chip_delay = 25,
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = falcon_hwcontrol,
.dev_ready = falcon_nand_ready,
}
};
static struct resource ltq_nand_res =
MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX);
static struct platform_device ltq_flash_nand = {
.name = "gen_nand",
.id = -1,
.num_resources = 1,
.resource = &ltq_nand_res,
.dev = {
.platform_data = &falcon_flash_nand_data,
},
};
void __init
falcon_register_nand(void)
{
platform_device_register(&ltq_flash_nand);
}
/* gpio */
#define DECLARE_GPIO_RES(port) \
static struct resource falcon_gpio ## port ## _res[] = { \
MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \
LTQ_GPIO ## port ## _SIZE), \
MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \
LTQ_PADCTRL ## port ## _SIZE), \
IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \
}
DECLARE_GPIO_RES(0);
DECLARE_GPIO_RES(1);
DECLARE_GPIO_RES(2);
DECLARE_GPIO_RES(3);
DECLARE_GPIO_RES(4);
void __init
falcon_register_gpio(void)
{
platform_device_register_simple("falcon_gpio", 0,
falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res));
platform_device_register_simple("falcon_gpio", 1,
falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res));
platform_device_register_simple("falcon_gpio", 2,
falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res));
}
void __init
falcon_register_gpio_extra(void)
{
platform_device_register_simple("falcon_gpio", 3,
falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res));
platform_device_register_simple("falcon_gpio", 4,
falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
}
/* spi flash */
static struct platform_device ltq_spi = {
.name = "falcon_spi",
.num_resources = 0,
};
void __init
falcon_register_spi_flash(struct spi_board_info *data)
{
spi_register_board_info(data, 1);
platform_device_register(&ltq_spi);
}
/* i2c */
static struct resource falcon_i2c_resources[] = {
MEM_RES("i2c", GPON_I2C_BASE, GPON_I2C_SIZE),
IRQ_RES(i2c_lb, FALCON_IRQ_I2C_LBREQ),
IRQ_RES(i2c_b, FALCON_IRQ_I2C_BREQ),
IRQ_RES(i2c_err, FALCON_IRQ_I2C_I2C_ERR),
IRQ_RES(i2c_p, FALCON_IRQ_I2C_I2C_P),
};
void __init
falcon_register_i2c(void)
{
platform_device_register_simple("i2c-falcon", 0,
falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
}

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target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.h Normal file
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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#ifndef _FALCON_DEVICES_H__
#define _FALCON_DEVICES_H__
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include "../devices.h"
extern void falcon_register_nand(void);
extern void falcon_register_gpio(void);
extern void falcon_register_gpio_extra(void);
extern void falcon_register_spi_flash(struct spi_board_info *data);
extern void falcon_register_i2c(void);
#endif

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target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <lantiq_soc.h>
/* Multiplexer Control Register */
#define LTQ_PADC_MUX(x) (x * 0x4)
/* Pad Control Availability Register */
#define LTQ_PADC_AVAIL 0x000000F0
/* Data Output Register */
#define LTQ_GPIO_OUT 0x00000000
/* Data Input Register */
#define LTQ_GPIO_IN 0x00000004
/* Direction Register */
#define LTQ_GPIO_DIR 0x00000008
/* External Interrupt Control Register 0 */
#define LTQ_GPIO_EXINTCR0 0x00000018
/* External Interrupt Control Register 1 */
#define LTQ_GPIO_EXINTCR1 0x0000001C
/* IRN Capture Register */
#define LTQ_GPIO_IRNCR 0x00000020
/* IRN Interrupt Configuration Register */
#define LTQ_GPIO_IRNCFG 0x0000002C
/* IRN Interrupt Enable Set Register */
#define LTQ_GPIO_IRNRNSET 0x00000030
/* IRN Interrupt Enable Clear Register */
#define LTQ_GPIO_IRNENCLR 0x00000034
/* Output Set Register */
#define LTQ_GPIO_OUTSET 0x00000040
/* Output Cler Register */
#define LTQ_GPIO_OUTCLR 0x00000044
/* Direction Clear Register */
#define LTQ_GPIO_DIRSET 0x00000048
/* Direction Set Register */
#define LTQ_GPIO_DIRCLR 0x0000004C
/* turn a gpio_chip into a falcon_gpio_port */
#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip)
/* turn a irq_data into a falcon_gpio_port */
#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg)
#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg)
#define ltq_pad_w32_mask(c, clear, set, reg) \
ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg)
#define ltq_port_r32(p, reg) ltq_r32(p->port + reg)
#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg)
#define ltq_port_w32_mask(p, clear, set, reg) \
ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg)
#define MAX_PORTS 5
#define PINS_PER_PORT 32
struct falcon_gpio_port {
struct gpio_chip gpio_chip;
void __iomem *pad;
void __iomem *port;
unsigned int irq_base;
unsigned int chained_irq;
struct clk *clk;
};
static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
int gpio_to_irq(unsigned int gpio)
{
return __gpio_to_irq(gpio);
}
EXPORT_SYMBOL(gpio_to_irq);
int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
{
int port = pin / 100;
int offset = pin % 100;
struct falcon_gpio_port *gpio_port;
if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS))
return -EINVAL;
gpio_port = &ltq_gpio_port[port];
ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset));
return 0;
}
EXPORT_SYMBOL(ltq_gpio_mux_set);
int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux,
unsigned int dir, const char *name)
{
int port = pin / 100;
int offset = pin % 100;
if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
return -EINVAL;
if (devm_gpio_request(dev, pin, name)) {
pr_err("failed to setup lantiq gpio: %s\n", name);
return -EBUSY;
}
if (dir)
gpio_direction_output(pin, 1);
else
gpio_direction_input(pin);
return ltq_gpio_mux_set(pin, mux);
}
EXPORT_SYMBOL(ltq_gpio_request);
static int
falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR);
return 0;
}
static void
falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
if (value)
ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET);
else
ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR);
}
static int
falcon_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
falcon_gpio_set(chip, offset, value);
ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET);
return 0;
}
static int
falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1)
return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1;
else
return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1;
}
static int
falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
{
if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
return -EBUSY;
/* switch on gpio function */
ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset));
return 0;
}
return -ENODEV;
}
static void
falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
{
if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
return;
/* switch off gpio function */
ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset));
}
}
static int
falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
return ctop(chip)->irq_base + offset;
}
static void
falcon_gpio_disable_irq(struct irq_data *d)
{
unsigned int offset = d->irq - itop(d)->irq_base;
ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
}
static void
falcon_gpio_enable_irq(struct irq_data *d)
{
unsigned int offset = d->irq - itop(d)->irq_base;
if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1)
/* switch on gpio function */
ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset));
ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET);
}
static void
falcon_gpio_ack_irq(struct irq_data *d)
{
unsigned int offset = d->irq - itop(d)->irq_base;
ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
}
static void
falcon_gpio_mask_and_ack_irq(struct irq_data *d)
{
unsigned int offset = d->irq - itop(d)->irq_base;
ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
}
static struct irq_chip falcon_gpio_irq_chip;
static int
falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
{
unsigned int offset = d->irq - itop(d)->irq_base;
unsigned int mask = 1 << offset;
if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
return 0;
if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
/* level triggered */
ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG);
irq_set_chip_and_handler_name(d->irq,
&falcon_gpio_irq_chip, handle_level_irq, "mux");
} else {
/* edge triggered */
ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG);
irq_set_chip_and_handler_name(d->irq,
&falcon_gpio_irq_chip, handle_simple_irq, "mux");
}
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1);
} else {
if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
/* positive logic: rising edge, high level */
ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
else
/* negative logic: falling edge, low level */
ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0);
ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1);
}
return gpio_direction_input(itop(d)->gpio_chip.base + offset);
}
static void
falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
unsigned long irncr;
int offset;
/* acknowledge interrupt */
irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR);
ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR);
desc->irq_data.chip->irq_ack(&desc->irq_data);
for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
generic_handle_irq(gpio_port->irq_base + offset);
}
static struct irq_chip falcon_gpio_irq_chip = {
.name = "gpio_irq_mux",
.irq_mask = falcon_gpio_disable_irq,
.irq_unmask = falcon_gpio_enable_irq,
.irq_ack = falcon_gpio_ack_irq,
.irq_mask_ack = falcon_gpio_mask_and_ack_irq,
.irq_set_type = falcon_gpio_irq_type,
};
static struct irqaction gpio_cascade = {
.handler = no_action,
.flags = IRQF_DISABLED,
.name = "gpio_cascade",
};
static int
falcon_gpio_probe(struct platform_device *pdev)
{
struct falcon_gpio_port *gpio_port;
int ret, i;
struct resource *gpiores, *padres;
int irq;
if (pdev->id >= MAX_PORTS)
return -ENODEV;
gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
irq = platform_get_irq(pdev, 0);
if (!gpiores || !padres)
return -ENODEV;
gpio_port = &ltq_gpio_port[pdev->id];
gpio_port->gpio_chip.label = "falcon-gpio";
gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
gpio_port->gpio_chip.get = falcon_gpio_get;
gpio_port->gpio_chip.set = falcon_gpio_set;
gpio_port->gpio_chip.request = falcon_gpio_request;
gpio_port->gpio_chip.free = falcon_gpio_free;
gpio_port->gpio_chip.base = 100 * pdev->id;
gpio_port->gpio_chip.ngpio = 32;
gpio_port->gpio_chip.dev = &pdev->dev;
gpio_port->port = ltq_remap_resource(gpiores);
gpio_port->pad = ltq_remap_resource(padres);
if (!gpio_port->port || !gpio_port->pad) {
dev_err(&pdev->dev, "Could not map io ranges\n");
ret = -ENOMEM;
goto err;
}
gpio_port->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(gpio_port->clk)) {
dev_err(&pdev->dev, "Could not get clock\n");
ret = PTR_ERR(gpio_port->clk);;
goto err;
}
clk_enable(gpio_port->clk);
if (irq > 0) {
/* irq_chip support */
gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id);
for (i = 0; i < 32; i++) {
irq_set_chip_and_handler_name(gpio_port->irq_base + i,
&falcon_gpio_irq_chip, handle_simple_irq,
"mux");
irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
/* set to negative logic (falling edge, low level) */
ltq_port_w32_mask(gpio_port, 0, 1 << i,
LTQ_GPIO_EXINTCR0);
}
gpio_port->chained_irq = irq;
setup_irq(irq, &gpio_cascade);
irq_set_handler_data(irq, gpio_port);
irq_set_chained_handler(irq, falcon_gpio_irq_handler);
}
ret = gpiochip_add(&gpio_port->gpio_chip);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
pdev->id, ret);
goto err;
}
platform_set_drvdata(pdev, gpio_port);
return ret;
err:
dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
if (gpiores)
release_resource(gpiores);
if (padres)
release_resource(padres);
if (gpio_port->port)
iounmap(gpio_port->port);
if (gpio_port->pad)
iounmap(gpio_port->pad);
return ret;
}
static struct platform_driver falcon_gpio_driver = {
.probe = falcon_gpio_probe,
.driver = {
.name = "falcon_gpio",
.owner = THIS_MODULE,
},
};
int __init
falcon_gpio_init(void)
{
int ret;
pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
ret = platform_driver_register(&falcon_gpio_driver);
if (ret)
pr_err("falcon_gpio: Error registering platform driver!");
return ret;
}
postcore_initcall(falcon_gpio_init);

138
target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98000.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
#include <linux/spi/eeprom.h>
#include "../machtypes.h"
#include "devices.h"
static struct mtd_partition easy98000_nor_partitions[] = {
{
.name = "uboot",
.offset = 0x0,
.size = 0x40000,
},
{
.name = "uboot_env",
.offset = 0x40000,
.size = 0x40000, /* 2 sectors for redundant env. */
},
{
.name = "linux",
.offset = 0x80000,
.size = 0xF80000, /* map only 16 MiB */
},
};
struct physmap_flash_data easy98000_nor_flash_data = {
.nr_parts = ARRAY_SIZE(easy98000_nor_partitions),
.parts = easy98000_nor_partitions,
};
static struct flash_platform_data easy98000_spi_flash_platform_data = {
.name = "sflash",
.parts = easy98000_nor_partitions,
.nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
};
static struct spi_board_info easy98000_spi_flash_data __initdata = {
.modalias = "m25p80",
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 10 * 1000 * 1000,
.mode = SPI_MODE_3,
.platform_data = &easy98000_spi_flash_platform_data
};
/* setup gpio based spi bus/device for access to the eeprom on the board */
#define SPI_GPIO_MRST 102
#define SPI_GPIO_MTSR 103
#define SPI_GPIO_CLK 104
#define SPI_GPIO_CS0 105
#define SPI_GPIO_CS1 106
#define SPI_GPIO_BUS_NUM 1
static struct spi_gpio_platform_data easy98000_spi_gpio_data = {
.sck = SPI_GPIO_CLK,
.mosi = SPI_GPIO_MTSR,
.miso = SPI_GPIO_MRST,
.num_chipselect = 2,
};
static struct platform_device easy98000_spi_gpio_device = {
.name = "spi_gpio",
.id = SPI_GPIO_BUS_NUM,
.dev.platform_data = &easy98000_spi_gpio_data,
};
static struct spi_eeprom at25160n = {
.byte_len = 16 * 1024 / 8,
.name = "at25160n",
.page_size = 32,
.flags = EE_ADDR2,
};
static struct spi_board_info easy98000_spi_gpio_devices __initdata = {
.modalias = "at25",
.bus_num = SPI_GPIO_BUS_NUM,
.max_speed_hz = 1000 * 1000,
.mode = SPI_MODE_3,
.chip_select = 1,
.controller_data = (void *) SPI_GPIO_CS1,
.platform_data = &at25160n,
};
static void __init
easy98000_init_common(void)
{
spi_register_board_info(&easy98000_spi_gpio_devices, 1);
platform_device_register(&easy98000_spi_gpio_device);
falcon_register_i2c();
}
static void __init
easy98000_init(void)
{
easy98000_init_common();
ltq_register_nor(&easy98000_nor_flash_data);
}
static void __init
easy98000sf_init(void)
{
easy98000_init_common();
falcon_register_spi_flash(&easy98000_spi_flash_data);
}
static void __init
easy98000nand_init(void)
{
easy98000_init_common();
falcon_register_nand();
}
MIPS_MACHINE(LANTIQ_MACH_EASY98000,
"EASY98000",
"EASY98000 Eval Board",
easy98000_init);
MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
"EASY98000SF",
"EASY98000 Eval Board (Serial Flash)",
easy98000sf_init);
MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
"EASY98000NAND",
"EASY98000 Eval Board (NAND Flash)",
easy98000nand_init);

84
target/linux/lantiq/files/arch/mips/lantiq/falcon/prom.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#include <lantiq_soc.h>
#include "devices.h"
#include "../prom.h"
#define SOC_FALCON "Falcon"
#define SOC_FALCON_D "Falcon-D"
#define SOC_FALCON_V "Falcon-V"
#define SOC_FALCON_M "Falcon-M"
#define PART_SHIFT 12
#define PART_MASK 0x0FFFF000
#define REV_SHIFT 28
#define REV_MASK 0xF0000000
#define SREV_SHIFT 22
#define SREV_MASK 0x03C00000
#define TYPE_SHIFT 26
#define TYPE_MASK 0x3C000000
/* this parameter allows us enable/disable asc1 via commandline */
static int register_asc1;
static int __init
ltq_parse_asc1(char *p)
{
register_asc1 = 1;
return 0;
}
__setup("use_asc1", ltq_parse_asc1);
void __init
ltq_soc_setup(void)
{
ltq_register_asc(0);
ltq_register_wdt();
falcon_register_gpio();
if (register_asc1)
ltq_register_asc(1);
}
void __init
ltq_soc_detect(struct ltq_soc_info *i)
{
u32 type;
i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
i->rev & 0x7, (i->srev & 0x3) + 1);
switch (i->partnum) {
case SOC_ID_FALCON:
type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
switch (type) {
case 0:
i->name = SOC_FALCON_D;
break;
case 1:
i->name = SOC_FALCON_V;
break;
case 2:
i->name = SOC_FALCON_M;
break;
default:
i->name = SOC_FALCON;
break;
}
i->type = SOC_TYPE_FALCON;
break;
default:
unreachable();
break;
}
}

87
target/linux/lantiq/files/arch/mips/lantiq/falcon/reset.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/pm.h>
#include <asm/reboot.h>
#include <linux/export.h>
#include <lantiq_soc.h>
/* CPU0 Reset Source Register */
#define LTQ_SYS1_CPU0RS 0x0040
/* reset cause mask */
#define LTQ_CPU0RS_MASK 0x0003
int
ltq_reset_cause(void)
{
return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK;
}
EXPORT_SYMBOL_GPL(ltq_reset_cause);
#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
#define BOOT_PW1 0x4C545100
#define BOOT_PW2 0x0051544C
#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
#define WDT_PW1 0x00BE0000
#define WDT_PW2 0x00DC0000
static void
ltq_machine_restart(char *command)
{
pr_notice("System restart\n");
local_irq_disable();
/* reboot magic */
ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
/* watchdog magic */
ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
ltq_w32(WDT_PW2 |
(0x3 << 26) | /* PWL */
(0x2 << 24) | /* CLKDIV */
(0x1 << 31) | /* enable */
(1), /* reload */
(void *)WDT_REG_BASE);
unreachable();
}
static void
ltq_machine_halt(void)
{
pr_notice("System halted.\n");
local_irq_disable();
unreachable();
}
static void
ltq_machine_power_off(void)
{
pr_notice("Please turn off the power now.\n");
local_irq_disable();
unreachable();
}
static int __init
mips_reboot_setup(void)
{
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
pm_power_off = ltq_machine_power_off;
return 0;
}
arch_initcall(mips_reboot_setup);

211
target/linux/lantiq/files/arch/mips/lantiq/falcon/sysctrl.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#include <linux/ioport.h>
#include <linux/export.h>
#include <linux/clkdev.h>
#include <asm/delay.h>
#include <lantiq_soc.h>
#include "devices.h"
#include "../clk.h"
/* infrastructure control register */
#define SYS1_INFRAC 0x00bc
/* Configuration fuses for drivers and pll */
#define STATUS_CONFIG 0x0040
/* GPE frequency selection */
#define GPPC_OFFSET 24
#define GPEFREQ_MASK 0x00000C0
#define GPEFREQ_OFFSET 10
/* Clock status register */
#define LTQ_SYSCTL_CLKS 0x0000
/* Clock enable register */
#define LTQ_SYSCTL_CLKEN 0x0004
/* Clock clear register */
#define LTQ_SYSCTL_CLKCLR 0x0008
/* Activation Status Register */
#define LTQ_SYSCTL_ACTS 0x0020
/* Activation Register */
#define LTQ_SYSCTL_ACT 0x0024
/* Deactivation Register */
#define LTQ_SYSCTL_DEACT 0x0028
/* reboot Register */
#define LTQ_SYSCTL_RBT 0x002c
/* CPU0 Clock Control Register */
#define LTQ_SYS1_CPU0CC 0x0040
/* clock divider bit */
#define LTQ_CPU0CC_CPUDIV 0x0001
static struct resource ltq_sysctl_res[] = {
MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE),
MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE),
};
static struct resource ltq_status_res =
MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE);
static struct resource ltq_ebu_res =
MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
static void __iomem *ltq_sysctl[3];
static void __iomem *ltq_status_membase;
void __iomem *ltq_sys1_membase;
void __iomem *ltq_ebu_membase;
#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y))
#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x))
#define ltq_reg_w32_mask(m, clear, set, reg) \
ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg)
#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y))
#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x))
static inline void
ltq_sysctl_wait(struct clk *clk,
unsigned int test, unsigned int reg)
{
int err = 1000000;
do {} while (--err && ((ltq_reg_r32(clk->module, reg)
& clk->bits) != test));
if (!err)
pr_err("module de/activation failed %d %08X %08X %08X\n",
clk->module, clk->bits, test,
ltq_reg_r32(clk->module, reg) & clk->bits);
}
static int
ltq_sysctl_activate(struct clk *clk)
{
ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN);
ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT);
ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS);
return 0;
}
static void
ltq_sysctl_deactivate(struct clk *clk)
{
ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR);
ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT);
ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS);
}
static int
ltq_sysctl_clken(struct clk *clk)
{
ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN);
ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS);
return 0;
}
static void
ltq_sysctl_clkdis(struct clk *clk)
{
ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR);
ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS);
}
static void
ltq_sysctl_reboot(struct clk *clk)
{
unsigned int act;
unsigned int bits;
act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT);
bits = ~act & clk->bits;
if (bits != 0) {
ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN);
ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT);
ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS);
}
ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT);
ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS);
}
/* enable the ONU core */
static void
ltq_gpe_enable(void)
{
unsigned int freq;
unsigned int status;
/* if if the clock is already enabled */
status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC);
if (status & (1 << (GPPC_OFFSET + 1)))
return;
if (ltq_status_r32(STATUS_CONFIG) == 0)
freq = 1; /* use 625MHz on unfused chip */
else
freq = (ltq_status_r32(STATUS_CONFIG) &
GPEFREQ_MASK) >>
GPEFREQ_OFFSET;
/* apply new frequency */
ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
udelay(1);
/* enable new frequency */
ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
udelay(1);
}
static inline void
clkdev_add_sys(const char *dev, unsigned int module,
unsigned int bits)
{
struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
clk->cl.dev_id = dev;
clk->cl.con_id = NULL;
clk->cl.clk = clk;
clk->module = module;
clk->bits = bits;
clk->activate = ltq_sysctl_activate;
clk->deactivate = ltq_sysctl_deactivate;
clk->enable = ltq_sysctl_clken;
clk->disable = ltq_sysctl_clkdis;
clk->reboot = ltq_sysctl_reboot;
clkdev_add(&clk->cl);
}
void __init
ltq_soc_init(void)
{
int i;
for (i = 0; i < 3; i++)
ltq_sysctl[i] = ltq_remap_resource(&ltq_sysctl_res[i]);
ltq_sys1_membase = ltq_sysctl[0];
ltq_status_membase = ltq_remap_resource(&ltq_status_res);
ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
ltq_gpe_enable();
/* get our 3 static rates for cpu, fpi and io clocks */
if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
else
clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
/* add our clock domains */
clkdev_add_sys("falcon_gpio.0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0);
clkdev_add_sys("falcon_gpio.1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
clkdev_add_sys("falcon_gpio.2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2);
clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3);
clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4);
clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT);
clkdev_add_sys("i2c-falcon.0", SYSCTL_SYS1, ACTS_I2C_ACT);
}

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target/linux/lantiq/files/arch/mips/lantiq/svip/Kconfig Normal file
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if SOC_SVIP
menu "Mips Machine"
config LANTIQ_MACH_EASY33016
bool "Easy33016"
default y
config LANTIQ_MACH_EASY336
select SYS_SUPPORTS_LITTLE_ENDIAN
bool "Easy336"
default y
endmenu
endif

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target/linux/lantiq/files/arch/mips/lantiq/svip/Makefile Normal file
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obj-y := devices.o prom.o reset.o clk-svip.o gpio.o dma.o switchip_setup.o pms.o mux.o
obj-$(CONFIG_LANTIQ_MACH_EASY33016) += mach-easy33016.o
obj-$(CONFIG_LANTIQ_MACH_EASY336) += mach-easy336.o

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target/linux/lantiq/files/arch/mips/lantiq/svip/clk-svip.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/time.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include <lantiq_soc.h>
#include <base_reg.h>
#include <sys0_reg.h>
#include <sys1_reg.h>
#include <status_reg.h>
static struct svip_reg_status *const status =
(struct svip_reg_status *)LTQ_STATUS_BASE;
static struct svip_reg_sys0 *const sys0 = (struct svip_reg_sys0 *)LTQ_SYS0_BASE;
static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE;
unsigned int ltq_svip_io_region_clock(void)
{
return 200000000; /* 200 MHz */
}
EXPORT_SYMBOL(ltq_svip_io_region_clock);
unsigned int ltq_svip_cpu_hz(void)
{
/* Magic BootROM speed location... */
if ((*(u32 *)0x9fc07ff0) == 1)
return *(u32 *)0x9fc07ff4;
if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) {
/* xT16 */
return 393216000;
} else {
switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) {
case 3:
return 475000000;
case 2:
return 450000000;
case 1:
return 425000000;
default:
return 400000000;
}
}
}
EXPORT_SYMBOL(ltq_svip_cpu_hz);
unsigned int ltq_svip_fpi_hz(void)
{
u32 fbs0_div[2] = {4, 8};
u32 div;
div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr));
return ltq_svip_cpu_hz()/fbs0_div[div];
}
EXPORT_SYMBOL(ltq_svip_fpi_hz);
unsigned int ltq_get_ppl_hz(void)
{
/* Magic BootROM speed location... */
if ((*(u32 *)0x9fc07ff0) == 1)
return *(u32 *)0x9fc07ff4;
if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) {
/* xT16 */
return 393216000;
} else {
switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) {
case 3:
return 475000000;
case 2:
return 450000000;
case 1:
return 425000000;
default:
return 400000000;
}
}
}
unsigned int ltq_get_fbs0_hz(void)
{
u32 fbs0_div[2] = {4, 8};
u32 div;
div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr));
return ltq_get_ppl_hz()/fbs0_div[div];
}
EXPORT_SYMBOL(ltq_get_fbs0_hz);

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#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/mtd/physmap.h>
#include <linux/kernel.h>
#include <linux/reboot.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/etherdevice.h>
#include <linux/reboot.h>
#include <linux/time.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/spi/spi.h>
#include <linux/mtd/nand.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <lantiq.h>
#include <base_reg.h>
#include <sys1_reg.h>
#include <sys2_reg.h>
#include <ebu_reg.h>
#include "devices.h"
#include <lantiq_soc.h>
#include <svip_mux.h>
#include <svip_pms.h>
/* ASC */
void __init svip_register_asc(int port)
{
switch (port) {
case 0:
ltq_register_asc(0);
svip_sys1_clk_enable(SYS1_CLKENR_ASC0);
break;
case 1:
ltq_register_asc(1);
svip_sys1_clk_enable(SYS1_CLKENR_ASC1);
break;
default:
break;
};
}
/* Ethernet */
static unsigned char svip_ethaddr[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
static struct platform_device ltq_mii = {
.name = "ifxmips_mii0",
.dev = {
.platform_data = svip_ethaddr,
},
};
static int __init svip_set_ethaddr(char *str)
{
sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
&svip_ethaddr[0], &svip_ethaddr[1], &svip_ethaddr[2],
&svip_ethaddr[3], &svip_ethaddr[4], &svip_ethaddr[5]);
return 0;
}
__setup("ethaddr=", svip_set_ethaddr);
void __init svip_register_eth(void)
{
if (!is_valid_ether_addr(svip_ethaddr))
random_ether_addr(svip_ethaddr);
platform_device_register(&ltq_mii);
svip_sys1_clk_enable(SYS1_CLKENR_ETHSW);
}
/* Virtual Ethernet */
static struct platform_device ltq_ve = {
.name = "ifxmips_svip_ve",
};
void __init svip_register_virtual_eth(void)
{
platform_device_register(&ltq_ve);
}
/* SPI */
static void __init ltq_register_ssc(int bus_num, unsigned long base, int irq_rx,
int irq_tx, int irq_err, int irq_frm)
{
struct resource res[] = {
{
.name = "regs",
.start = base,
.end = base + 0x20 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "rx",
.start = irq_rx,
.flags = IORESOURCE_IRQ,
}, {
.name = "tx",
.start = irq_tx,
.flags = IORESOURCE_IRQ,
}, {
.name = "err",
.start = irq_err,
.flags = IORESOURCE_IRQ,
}, {
.name = "frm",
.start = irq_frm,
.flags = IORESOURCE_IRQ,
},
};
platform_device_register_simple("ifx_ssc", bus_num, res,
ARRAY_SIZE(res));
}
static struct spi_board_info bdinfo[] __initdata = {
{
.modalias = "xt16",
.mode = SPI_MODE_3,
.irq = INT_NUM_IM5_IRL0 + 28,
.max_speed_hz = 1000000,
.bus_num = 0,
.chip_select = 1,
},
{
.modalias = "xt16",
.mode = SPI_MODE_3,
.irq = INT_NUM_IM5_IRL0 + 19,
.max_speed_hz = 1000000,
.bus_num = 0,
.chip_select = 2,
},
{
.modalias = "loop",
.mode = SPI_MODE_0 | SPI_LOOP,
.irq = -1,
.max_speed_hz = 10000000,
.bus_num = 0,
.chip_select = 3,
},
};
void __init svip_register_spi(void)
{
ltq_register_ssc(0, LTQ_SSC0_BASE, INT_NUM_IM1_IRL0 + 6,
INT_NUM_IM1_IRL0 + 7, INT_NUM_IM1_IRL0 + 8,
INT_NUM_IM1_IRL0 + 9);
ltq_register_ssc(1, LTQ_SSC1_BASE, INT_NUM_IM1_IRL0 + 10,
INT_NUM_IM1_IRL0 + 11, INT_NUM_IM1_IRL0 + 12,
INT_NUM_IM1_IRL0 + 13);
spi_register_board_info(bdinfo, ARRAY_SIZE(bdinfo));
svip_sys1_clk_enable(SYS1_CLKENR_SSC0 | SYS1_CLKENR_SSC1);
}
void __init svip_register_spi_flash(struct spi_board_info *bdinfo)
{
spi_register_board_info(bdinfo, 1);
}
/* GPIO */
static struct platform_device ltq_gpio = {
.name = "ifxmips_gpio",
};
static struct platform_device ltq_gpiodev = {
.name = "GPIODEV",
};
void __init svip_register_gpio(void)
{
platform_device_register(&ltq_gpio);
platform_device_register(&ltq_gpiodev);
}
/* MUX */
static struct ltq_mux_settings ltq_mux_settings;
static struct platform_device ltq_mux = {
.name = "ltq_mux",
.dev = {
.platform_data = &ltq_mux_settings,
}
};
void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS],
const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS],
const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS],
const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS],
const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS])
{
ltq_mux_settings.mux_p0 = mux_p0;
ltq_mux_settings.mux_p1 = mux_p1;
ltq_mux_settings.mux_p2 = mux_p2;
ltq_mux_settings.mux_p3 = mux_p3;
ltq_mux_settings.mux_p4 = mux_p4;
if (mux_p0)
svip_sys1_clk_enable(SYS1_CLKENR_PORT0);
if (mux_p1)
svip_sys1_clk_enable(SYS1_CLKENR_PORT1);
if (mux_p2)
svip_sys1_clk_enable(SYS1_CLKENR_PORT2);
if (mux_p3)
svip_sys1_clk_enable(SYS1_CLKENR_PORT3);
if (mux_p4)
svip_sys2_clk_enable(SYS2_CLKENR_PORT4);
platform_device_register(&ltq_mux);
}
/* NAND */
#define NAND_ADDR_REGION_BASE (LTQ_EBU_SEG1_BASE)
#define NAND_CLE_BIT (1 << 3)
#define NAND_ALE_BIT (1 << 2)
static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE;
static int svip_nand_probe(struct platform_device *pdev)
{
ebu_w32(LTQ_EBU_ADDR_SEL_0_BASE_VAL(CPHYSADDR(NAND_ADDR_REGION_BASE)
>> 12)
| LTQ_EBU_ADDR_SEL_0_MASK_VAL(15)
| LTQ_EBU_ADDR_SEL_0_MRME_VAL(0)
| LTQ_EBU_ADDR_SEL_0_REGEN_VAL(1),
addr_sel_0);
ebu_w32(LTQ_EBU_CON_0_WRDIS_VAL(0)
| LTQ_EBU_CON_0_ADSWP_VAL(1)
| LTQ_EBU_CON_0_AGEN_VAL(0x00)
| LTQ_EBU_CON_0_SETUP_VAL(1)
| LTQ_EBU_CON_0_WAIT_VAL(0x00)
| LTQ_EBU_CON_0_WINV_VAL(0)
| LTQ_EBU_CON_0_PW_VAL(0x00)
| LTQ_EBU_CON_0_ALEC_VAL(0)
| LTQ_EBU_CON_0_BCGEN_VAL(0x01)
| LTQ_EBU_CON_0_WAITWRC_VAL(1)
| LTQ_EBU_CON_0_WAITRDC_VAL(1)
| LTQ_EBU_CON_0_HOLDC_VAL(1)
| LTQ_EBU_CON_0_RECOVC_VAL(0)
| LTQ_EBU_CON_0_CMULT_VAL(0x01),
con_0);
/*
* ECC disabled
* CLE, ALE and CS are pulse, all other signal are latches based
* CLE and ALE are active high, PRE, WP, SE and CS/CE are active low
* OUT_CS_S is disabled
* NAND mode is disabled
*/
ebu_w32(LTQ_EBU_NAND_CON_ECC_ON_VAL(0)
| LTQ_EBU_NAND_CON_LAT_EN_VAL(0x38)
| LTQ_EBU_NAND_CON_OUT_CS_S_VAL(0)
| LTQ_EBU_NAND_CON_IN_CS_S_VAL(0)
| LTQ_EBU_NAND_CON_PRE_P_VAL(1)
| LTQ_EBU_NAND_CON_WP_P_VAL(1)
| LTQ_EBU_NAND_CON_SE_P_VAL(1)
| LTQ_EBU_NAND_CON_CS_P_VAL(1)
| LTQ_EBU_NAND_CON_CLE_P_VAL(0)
| LTQ_EBU_NAND_CON_ALE_P_VAL(0)
| LTQ_EBU_NAND_CON_CSMUX_E_VAL(0)
| LTQ_EBU_NAND_CON_NANDMODE_VAL(0),
nand_con);
return 0;
}
static void svip_nand_hwcontrol(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
unsigned long adr;
/* Coming here means to change either the enable state or
* the address for controlling ALE or CLE */
/* NAND_NCE: Select the chip by setting nCE to low.
* This is done in CON register */
if (ctrl & NAND_NCE)
ebu_w32_mask(0, LTQ_EBU_NAND_CON_NANDMODE_VAL(1),
nand_con);
else
ebu_w32_mask(LTQ_EBU_NAND_CON_NANDMODE_VAL(1),
0, nand_con);
/* The addressing of CLE or ALE is done via different addresses.
We are now changing the address depending on the given action
SVIPs NAND_CLE_BIT = (1 << 3), NAND_CLE = 0x02
NAND_ALE_BIT = (1 << 2) = NAND_ALE (0x04) */
adr = (unsigned long)this->IO_ADDR_W;
adr &= ~(NAND_CLE_BIT | NAND_ALE_BIT);
adr |= (ctrl & NAND_CLE) << 2 | (ctrl & NAND_ALE);
this->IO_ADDR_W = (void __iomem *)adr;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int svip_nand_ready(struct mtd_info *mtd)
{
return (ebu_r32(nand_wait) & 0x01) == 0x01;
}
static inline void svip_nand_wait(void)
{
static const int nops = 150;
int i;
for (i = 0; i < nops; i++)
asm("nop");
}
static void svip_nand_write_buf(struct mtd_info *mtd,
const u_char *buf, int len)
{
int i;
struct nand_chip *this = mtd->priv;
for (i = 0; i < len; i++) {
writeb(buf[i], this->IO_ADDR_W);
svip_nand_wait();
}
}
static void svip_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
int i;
struct nand_chip *this = mtd->priv;
for (i = 0; i < len; i++) {
buf[i] = readb(this->IO_ADDR_R);
svip_nand_wait();
}
}
static const char *part_probes[] = { "cmdlinepart", NULL };
static struct platform_nand_data svip_flash_nand_data = {
.chip = {
.nr_chips = 1,
.part_probe_types = part_probes,
},
.ctrl = {
.probe = svip_nand_probe,
.cmd_ctrl = svip_nand_hwcontrol,
.dev_ready = svip_nand_ready,
.write_buf = svip_nand_write_buf,
.read_buf = svip_nand_read_buf,
}
};
static struct resource svip_nand_resources[] = {
MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX),
};
static struct platform_device svip_flash_nand = {
.name = "gen_nand",
.id = -1,
.num_resources = ARRAY_SIZE(svip_nand_resources),
.resource = svip_nand_resources,
.dev = {
.platform_data = &svip_flash_nand_data,
},
};
void __init svip_register_nand(void)
{
platform_device_register(&svip_flash_nand);
}

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target/linux/lantiq/files/arch/mips/lantiq/svip/devices.h Normal file
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#ifndef _SVIP_DEVICES_H__
#define _SVIP_DEVICES_H__
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <svip_mux.h>
#include "../devices.h"
extern void __init svip_register_asc(int port);
extern void __init svip_register_eth(void);
extern void __init svip_register_virtual_eth(void);
extern void __init svip_register_spi(void);
extern void __init svip_register_spi_flash(struct spi_board_info *bdinfo);
extern void __init svip_register_gpio(void);
extern void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS],
const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS],
const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS],
const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS],
const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]);
extern void __init svip_register_nand(void);
#endif

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target/linux/lantiq/files/arch/mips/lantiq/svip/dma.c Normal file
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target/linux/lantiq/files/arch/mips/lantiq/svip/gpio.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/proc_fs.h>
#include <linux/init.h>
#include <linux/ioctl.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/kobject.h>
#include <linux/workqueue.h>
#include <linux/skbuff.h>
#include <linux/netlink.h>
#include <linux/platform_device.h>
#include <net/sock.h>
#include <linux/uaccess.h>
#include <linux/version.h>
#include <linux/semaphore.h>
#include <lantiq_soc.h>
#include <svip_mux.h>
#include <base_reg.h>
#include <port_reg.h>
#define DRV_NAME "ifxmips_gpio"
int gpio_to_irq(unsigned int gpio)
{
return -EINVAL;
}
EXPORT_SYMBOL(gpio_to_irq);
int irq_to_gpio(unsigned int gpio)
{
return -EINVAL;
}
EXPORT_SYMBOL(irq_to_gpio);
struct ltq_port_base {
struct svip_reg_port *base;
u32 pins;
};
/* Base addresses for ports */
static const struct ltq_port_base ltq_port_base[] = {
{ (struct svip_reg_port *)LTQ_PORT_P0_BASE, 20 },
{ (struct svip_reg_port *)LTQ_PORT_P1_BASE, 20 },
{ (struct svip_reg_port *)LTQ_PORT_P2_BASE, 19 },
{ (struct svip_reg_port *)LTQ_PORT_P3_BASE, 20 },
{ (struct svip_reg_port *)LTQ_PORT_P4_BASE, 24 }
};
#define MAX_PORTS ARRAY_SIZE(ltq_port_base)
#define PINS_PER_PORT(port) (ltq_port_base[port].pins)
static inline
void ltq_port_set_exintcr0(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->exintcr0) | (1 << pin),
ltq_port_base[port].base->exintcr0);
}
static inline
void ltq_port_clear_exintcr0(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->exintcr0) & ~(1 << pin),
ltq_port_base[port].base->exintcr0);
}
static inline
void ltq_port_set_exintcr1(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->exintcr1) | (1 << pin),
ltq_port_base[port].base->exintcr1);
}
static inline
void ltq_port_clear_exintcr1(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->exintcr1) & ~(1 << pin),
ltq_port_base[port].base->exintcr1);
}
static inline
void ltq_port_set_irncfg(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->irncfg) | (1 << pin),
ltq_port_base[port].base->irncfg);
}
static inline
void ltq_port_clear_irncfg(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->irncfg) & ~(1 << pin),
ltq_port_base[port].base->irncfg);
}
static inline
void ltq_port_set_irnen(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(1 << pin, ltq_port_base[port].base->irnenset);
}
static inline
void ltq_port_clear_irnen(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(1 << pin, ltq_port_base[port].base->irnenclr);
}
static inline
void ltq_port_set_dir_out(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->dir) | (1 << pin),
ltq_port_base[port].base->dir);
}
static inline
void ltq_port_set_dir_in(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->dir) & ~(1 << pin),
ltq_port_base[port].base->dir);
}
static inline
void ltq_port_set_output(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->out) | (1 << pin),
ltq_port_base[port].base->out);
}
static inline
void ltq_port_clear_output(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->out) & ~(1 << pin),
ltq_port_base[port].base->out);
}
static inline
int ltq_port_get_input(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return -EINVAL;
return (port_r32(ltq_port_base[port].base->in) & (1 << pin)) == 0;
}
static inline
void ltq_port_set_puen(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->puen) | (1 << pin),
ltq_port_base[port].base->puen);
}
static inline
void ltq_port_clear_puen(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->puen) & ~(1 << pin),
ltq_port_base[port].base->puen);
}
static inline
void ltq_port_set_altsel0(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->altsel0) | (1 << pin),
ltq_port_base[port].base->altsel0);
}
static inline
void ltq_port_clear_altsel0(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->altsel0) & ~(1 << pin),
ltq_port_base[port].base->altsel0);
}
static inline
void ltq_port_set_altsel1(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->altsel1) | (1 << pin),
ltq_port_base[port].base->altsel1);
}
static inline
void ltq_port_clear_altsel1(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return;
port_w32(port_r32(ltq_port_base[port].base->altsel1) & ~(1 << pin),
ltq_port_base[port].base->altsel1);
}
void ltq_gpio_configure(int port, int pin, bool dirin, bool puen,
bool altsel0, bool altsel1)
{
if (dirin)
ltq_port_set_dir_in(port, pin);
else
ltq_port_set_dir_out(port, pin);
if (puen)
ltq_port_set_puen(port, pin);
else
ltq_port_clear_puen(port, pin);
if (altsel0)
ltq_port_set_altsel0(port, pin);
else
ltq_port_clear_altsel0(port, pin);
if (altsel1)
ltq_port_set_altsel1(port, pin);
else
ltq_port_clear_altsel1(port, pin);
}
int ltq_port_get_dir(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return -EINVAL;
return (port_r32(ltq_port_base[port].base->dir) & (1 << pin)) != 0;
}
int ltq_port_get_puden(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return -EINVAL;
return (port_r32(ltq_port_base[port].base->puen) & (1 << pin)) != 0;
}
int ltq_port_get_altsel0(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return -EINVAL;
return (port_r32(ltq_port_base[port].base->altsel0) & (1 << pin)) != 0;
}
int ltq_port_get_altsel1(unsigned int port, unsigned int pin)
{
if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port))
return -EINVAL;
return (port_r32(ltq_port_base[port].base->altsel1) & (1 << pin)) != 0;
}
struct ltq_gpio_port {
struct gpio_chip gpio_chip;
unsigned int irq_base;
unsigned int chained_irq;
};
static struct ltq_gpio_port ltq_gpio_port[MAX_PORTS];
static int gpio_exported;
static int __init gpio_export_setup(char *str)
{
get_option(&str, &gpio_exported);
return 1;
}
__setup("gpio_exported=", gpio_export_setup);
static inline unsigned int offset2port(unsigned int offset)
{
unsigned int i;
unsigned int prev = 0;
for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) {
if (offset >= prev &&
offset < prev + ltq_port_base[i].pins)
return i;
prev = ltq_port_base[i].pins;
}
return 0;
}
static inline unsigned int offset2pin(unsigned int offset)
{
unsigned int i;
unsigned int prev = 0;
for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) {
if (offset >= prev &&
offset < prev + ltq_port_base[i].pins)
return offset - prev;
prev = ltq_port_base[i].pins;
}
return 0;
}
static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
ltq_port_set_dir_in(offset2port(offset), offset2pin(offset));
return 0;
}
static int ltq_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
ltq_port_set_dir_out(offset2port(offset), offset2pin(offset));
return 0;
}
static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
return ltq_port_get_input(offset2port(offset), offset2pin(offset));
}
static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
if (value)
ltq_port_set_output(offset2port(offset), offset2pin(offset));
else
ltq_port_clear_output(offset2port(offset), offset2pin(offset));
}
static int svip_gpio_request(struct gpio_chip *chip, unsigned offset)
{
return 0;
}
static void ltq_gpio_free(struct gpio_chip *chip, unsigned offset)
{
}
static int ltq_gpio_probe(struct platform_device *pdev)
{
int ret = 0;
struct ltq_gpio_port *gpio_port;
if (pdev->id >= MAX_PORTS)
return -ENODEV;
gpio_port = &ltq_gpio_port[pdev->id];
gpio_port->gpio_chip.label = "ltq-gpio";
gpio_port->gpio_chip.direction_input = ltq_gpio_direction_input;
gpio_port->gpio_chip.direction_output = ltq_gpio_direction_output;
gpio_port->gpio_chip.get = ltq_gpio_get;
gpio_port->gpio_chip.set = ltq_gpio_set;
gpio_port->gpio_chip.request = svip_gpio_request;
gpio_port->gpio_chip.free = ltq_gpio_free;
gpio_port->gpio_chip.base = 100 * pdev->id;
gpio_port->gpio_chip.ngpio = 32;
gpio_port->gpio_chip.dev = &pdev->dev;
gpio_port->gpio_chip.exported = gpio_exported;
ret = gpiochip_add(&gpio_port->gpio_chip);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
pdev->id, ret);
goto err;
}
platform_set_drvdata(pdev, gpio_port);
return 0;
err:
return ret;
}
static int ltq_gpio_remove(struct platform_device *pdev)
{
struct ltq_gpio_port *gpio_port = platform_get_drvdata(pdev);
int ret;
ret = gpiochip_remove(&gpio_port->gpio_chip);
return ret;
}
static struct platform_driver ltq_gpio_driver = {
.probe = ltq_gpio_probe,
.remove = __devexit_p(ltq_gpio_remove),
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
},
};
int __init ltq_gpio_init(void)
{
int ret = platform_driver_register(&ltq_gpio_driver);
if (ret)
printk(KERN_INFO DRV_NAME
": Error registering platform driver!");
return ret;
}
postcore_initcall(ltq_gpio_init);
/**
* Convert interrupt number to corresponding port/pin pair
* Returns the port/pin pair serving the selected external interrupt;
* needed since mapping not linear.
*
* \param exint External interrupt number
* \param port Pointer for resulting port
* \param pin Pointer for resutling pin
* \return -EINVAL Invalid exint
* \return 0 port/pin updated
* \ingroup API
*/
static int ltq_exint2port(u32 exint, int *port, int *pin)
{
if ((exint >= 0) && (exint <= 10)) {
*port = 0;
*pin = exint + 7;
} else if ((exint >= 11) && (exint <= 14)) {
*port = 1;
*pin = 18 - (exint - 11) ;
} else if (exint == 15) {
*port = 1;
*pin = 19;
} else if (exint == 16) {
*port = 0;
*pin = 19;
} else {
return -EINVAL;
}
return 0;
}
/**
* Enable external interrupt.
* This function enables an external interrupt and sets the given mode.
* valid values for mode are:
* - 0 = Interrupt generation disabled
* - 1 = Interrupt on rising edge
* - 2 = Interrupt on falling edge
* - 3 = Interrupt on rising and falling edge
* - 5 = Interrupt on high level detection
* - 6 = Interrupt on low level detection
*
* \param exint - Number of external interrupt
* \param mode - Trigger mode
* \return 0 on success
* \ingroup API
*/
int ifx_enable_external_int(u32 exint, u32 mode)
{
int port;
int pin;
if ((mode < 0) || (mode > 6))
return -EINVAL;
if (ltq_exint2port(exint, &port, &pin))
return -EINVAL;
ltq_port_clear_exintcr0(port, pin);
ltq_port_clear_exintcr1(port, pin);
ltq_port_clear_irncfg(port, pin);
if (mode & 0x1)
ltq_port_set_exintcr0(port, pin);
if (mode & 0x2)
ltq_port_set_exintcr1(port, pin);
if (mode & 0x4)
ltq_port_set_irncfg(port, pin);
ltq_port_set_irnen(port, pin);
return 0;
}
EXPORT_SYMBOL(ifx_enable_external_int);
/**
* Disable external interrupt.
* This function disables an external interrupt and sets mode to 0x00.
*
* \param exint - Number of external interrupt
* \return 0 on success
* \ingroup API
*/
int ifx_disable_external_int(u32 exint)
{
int port;
int pin;
if (ltq_exint2port(exint, &port, &pin))
return -EINVAL;
ltq_port_clear_irnen(port, pin);
return 0;
}
EXPORT_SYMBOL(ifx_disable_external_int);

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target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy33016.c Normal file
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#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/gpio_buttons.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include "../machtypes.h"
#include <sys1_reg.h>
#include <sys2_reg.h>
#include <svip_pms.h>
#include "devices.h"
static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = {
LTQ_MUX_P0_0_SSC0_MTSR,
LTQ_MUX_P0_1_SSC0_MRST,
LTQ_MUX_P0_2_SSC0_SCLK,
LTQ_MUX_P0_3_SSC1_MTSR,
LTQ_MUX_P0_4_SSC1_MRST,
LTQ_MUX_P0_5_SSC1_SCLK,
LTQ_MUX_P0_6_SSC0_CS0,
LTQ_MUX_P0_7_SSC0_CS1,
LTQ_MUX_P0_8_SSC0_CS2,
LTQ_MUX_P0_9,
LTQ_MUX_P0_10,
LTQ_MUX_P0_11_EXINT4,
LTQ_MUX_P0_12,
LTQ_MUX_P0_13,
LTQ_MUX_P0_14_ASC0_TXD,
LTQ_MUX_P0_15_ASC0_RXD,
LTQ_MUX_P0_16_EXINT9,
LTQ_MUX_P0_17_EXINT10,
LTQ_MUX_P0_18_EJ_BRKIN,
LTQ_MUX_P0_19_EXINT16
};
static void __init easy33016_init(void)
{
svip_sys1_clk_enable(SYS1_CLKENR_L2C |
SYS1_CLKENR_DDR2 |
SYS1_CLKENR_SMI2 |
SYS1_CLKENR_SMI1 |
SYS1_CLKENR_SMI0 |
SYS1_CLKENR_FMI0 |
SYS1_CLKENR_DMA |
SYS1_CLKENR_SSC0 |
SYS1_CLKENR_SSC1 |
SYS1_CLKENR_EBU);
svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC |
SYS2_CLKENR_MBS |
SYS2_CLKENR_SWINT);
svip_register_mux(mux_p0, NULL, NULL, NULL, NULL);
svip_register_asc(0);
svip_register_eth();
svip_register_virtual_eth();
ltq_register_wdt();
svip_register_gpio();
svip_register_spi();
svip_register_nand();
}
MIPS_MACHINE(LANTIQ_MACH_EASY33016,
"EASY33016",
"EASY33016",
easy33016_init);

221
target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy336.c Normal file
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#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/gpio_buttons.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include "../machtypes.h"
#include <sys1_reg.h>
#include <sys2_reg.h>
#include <svip_pms.h>
#include "devices.h"
static struct mtd_partition easy336_sflash_partitions[] = {
{
.name = "SPI flash",
.size = MTDPART_SIZ_FULL,
.offset = 0,
},
};
static struct flash_platform_data easy336_sflash_data = {
.name = "m25p32",
.parts = (void *)&easy336_sflash_partitions,
.nr_parts = ARRAY_SIZE(easy336_sflash_partitions),
.type = "m25p32",
};
static struct spi_board_info bdinfo[] __initdata = {
{
.modalias = "m25p80",
.platform_data = &easy336_sflash_data,
.mode = SPI_MODE_0,
.irq = -1,
.max_speed_hz = 25000000,
.bus_num = 0,
.chip_select = 0,
}
};
static struct mtd_partition easy336_partitions[] = {
{
.name = "uboot",
.offset = 0x0,
.size = 0x40000,
},
{
.name = "uboot_env",
.offset = 0x40000,
.size = 0x20000,
},
{
.name = "linux",
.offset = 0x60000,
.size = 0x1a0000,
},
{
.name = "rootfs",
.offset = 0x200000,
.size = 0x500000,
},
};
static struct physmap_flash_data easy336_flash_data = {
.nr_parts = ARRAY_SIZE(easy336_partitions),
.parts = easy336_partitions,
};
static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = {
LTQ_MUX_P0_0_SSC0_MTSR,
LTQ_MUX_P0_1_SSC0_MRST,
LTQ_MUX_P0_2_SSC0_SCLK,
LTQ_MUX_P0_3_SSC1_MTSR,
LTQ_MUX_P0_4_SSC1_MRST,
LTQ_MUX_P0_5_SSC1_SCLK,
LTQ_MUX_P0_6_SSC0_CS0,
LTQ_MUX_P0_7_SSC0_CS1,
LTQ_MUX_P0_8_SSC0_CS2,
LTQ_MUX_P0_9_SSC0_CS3,
LTQ_MUX_P0_10_SSC0_CS4,
LTQ_MUX_P0_11_SSC0_CS5,
LTQ_MUX_P0_12_EXINT5,
LTQ_MUX_P0_13_EXINT6,
LTQ_MUX_P0_14_ASC0_TXD,
LTQ_MUX_P0_15_ASC0_RXD,
LTQ_MUX_P0_16_EXINT9,
LTQ_MUX_P0_17_EXINT10,
LTQ_MUX_P0_18_EJ_BRKIN,
LTQ_MUX_P0_19_EXINT16
};
static const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS] = {
LTQ_MUX_P2_0_EBU_A0,
LTQ_MUX_P2_1_EBU_A1,
LTQ_MUX_P2_2_EBU_A2,
LTQ_MUX_P2_3_EBU_A3,
LTQ_MUX_P2_4_EBU_A4,
LTQ_MUX_P2_5_EBU_A5,
LTQ_MUX_P2_6_EBU_A6,
LTQ_MUX_P2_7_EBU_A7,
LTQ_MUX_P2_8_EBU_A8,
LTQ_MUX_P2_9_EBU_A9,
LTQ_MUX_P2_10_EBU_A10,
LTQ_MUX_P2_11_EBU_A11,
LTQ_MUX_P2_12_EBU_RD,
LTQ_MUX_P2_13_EBU_WR,
LTQ_MUX_P2_14_EBU_ALE,
LTQ_MUX_P2_15_EBU_WAIT,
LTQ_MUX_P2_16_EBU_RDBY,
LTQ_MUX_P2_17_EBU_BC0,
LTQ_MUX_P2_18_EBU_BC1
};
static const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS] = {
LTQ_MUX_P3_0_EBU_AD0,
LTQ_MUX_P3_1_EBU_AD1,
LTQ_MUX_P3_2_EBU_AD2,
LTQ_MUX_P3_3_EBU_AD3,
LTQ_MUX_P3_4_EBU_AD4,
LTQ_MUX_P3_5_EBU_AD5,
LTQ_MUX_P3_6_EBU_AD6,
LTQ_MUX_P3_7_EBU_AD7,
LTQ_MUX_P3_8_EBU_AD8,
LTQ_MUX_P3_9_EBU_AD9,
LTQ_MUX_P3_10_EBU_AD10,
LTQ_MUX_P3_11_EBU_AD11,
LTQ_MUX_P3_12_EBU_AD12,
LTQ_MUX_P3_13_EBU_AD13,
LTQ_MUX_P3_14_EBU_AD14,
LTQ_MUX_P3_15_EBU_AD15,
LTQ_MUX_P3_16_EBU_CS0,
LTQ_MUX_P3_17_EBU_CS1,
LTQ_MUX_P3_18_EBU_CS2,
LTQ_MUX_P3_19_EBU_CS3
};
static void __init easy336_init_common(void)
{
svip_sys1_clk_enable(SYS1_CLKENR_L2C |
SYS1_CLKENR_DDR2 |
SYS1_CLKENR_SMI2 |
SYS1_CLKENR_SMI1 |
SYS1_CLKENR_SMI0 |
SYS1_CLKENR_FMI0 |
SYS1_CLKENR_DMA |
SYS1_CLKENR_GPTC |
SYS1_CLKENR_EBU);
svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC |
SYS2_CLKENR_MBS |
SYS2_CLKENR_SWINT |
SYS2_CLKENR_HWACC3 |
SYS2_CLKENR_HWACC2 |
SYS2_CLKENR_HWACC1 |
SYS2_CLKENR_HWACC0 |
SYS2_CLKENR_SIF7 |
SYS2_CLKENR_SIF6 |
SYS2_CLKENR_SIF5 |
SYS2_CLKENR_SIF4 |
SYS2_CLKENR_SIF3 |
SYS2_CLKENR_SIF2 |
SYS2_CLKENR_SIF1 |
SYS2_CLKENR_SIF0 |
SYS2_CLKENR_DFEV7 |
SYS2_CLKENR_DFEV6 |
SYS2_CLKENR_DFEV5 |
SYS2_CLKENR_DFEV4 |
SYS2_CLKENR_DFEV3 |
SYS2_CLKENR_DFEV2 |
SYS2_CLKENR_DFEV1 |
SYS2_CLKENR_DFEV0);
svip_register_mux(mux_p0, NULL, mux_p2, mux_p3, NULL);
svip_register_asc(0);
svip_register_eth();
svip_register_virtual_eth();
/* ltq_register_wdt(); - conflicts with lq_switch */
svip_register_gpio();
svip_register_spi();
ltq_register_tapi();
}
static void __init easy336_init(void)
{
easy336_init_common();
ltq_register_nor(&easy336_flash_data);
}
static void __init easy336sf_init(void)
{
easy336_init_common();
svip_register_spi_flash(bdinfo);
}
static void __init easy336nand_init(void)
{
easy336_init_common();
svip_register_nand();
}
MIPS_MACHINE(LANTIQ_MACH_EASY336,
"EASY336",
"EASY336",
easy336_init);
MIPS_MACHINE(LANTIQ_MACH_EASY336SF,
"EASY336SF",
"EASY336 (Serial Flash)",
easy336sf_init);
MIPS_MACHINE(LANTIQ_MACH_EASY336NAND,
"EASY336NAND",
"EASY336 (NAND Flash)",
easy336nand_init);

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/************************************************************************
*
* Copyright (c) 2007
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/proc_fs.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#include <linux/platform_device.h>
#include <lantiq_soc.h>
#include <svip_mux.h>
#include <sys1_reg.h>
#include <sys2_reg.h>
#include <svip_pms.h>
#define DRV_NAME "ltq_mux"
static void ltq_mux_port_init(const int port,
const struct ltq_mux_pin *pins,
const int pin_max)
{
unsigned int i;
for (i = 0; i < pin_max; i++)
ltq_gpio_configure(port,
i,
pins[i].dirin,
pins[i].puen,
pins[i].altsel0,
pins[i].altsel1);
}
static int ltq_mux_probe(struct platform_device *pdev)
{
struct ltq_mux_settings *mux_settings = dev_get_platdata(&pdev->dev);
if (mux_settings->mux_p0)
ltq_mux_port_init(0,
mux_settings->mux_p0,
LTQ_MUX_P0_PINS);
if (mux_settings->mux_p1)
ltq_mux_port_init(1,
mux_settings->mux_p1,
LTQ_MUX_P1_PINS);
if (mux_settings->mux_p2)
ltq_mux_port_init(2,
mux_settings->mux_p2,
LTQ_MUX_P2_PINS);
if (mux_settings->mux_p3)
ltq_mux_port_init(3,
mux_settings->mux_p3,
LTQ_MUX_P3_PINS);
if (mux_settings->mux_p4)
ltq_mux_port_init(4,
mux_settings->mux_p4,
LTQ_MUX_P4_PINS);
return 0;
}
int ltq_mux_read_procmem(char *buf, char **start, off_t offset,
int count, int *eof, void *data)
{
int len = 0;
int t = 0, i = 0;
u32 port_clk[5] = {
SYS1_CLKENR_PORT0,
SYS1_CLKENR_PORT1,
SYS1_CLKENR_PORT2,
SYS1_CLKENR_PORT3,
SYS2_CLKENR_PORT4,
};
#define PROC_PRINT(fmt, args...) \
do { \
int c_len = 0; \
c_len = snprintf(buf + len, count - len, fmt, ## args); \
if (c_len <= 0) \
goto out; \
if (c_len >= (count - len)) { \
len += (count - len); \
goto out; \
} \
len += c_len; \
if (offset > 0) { \
if (len > offset) { \
len -= offset; \
memmove(buf, buf + offset, len); \
offset = 0; \
} else { \
offset -= len; \
len = 0; \
} \
} \
} while (0)
PROC_PRINT("\nVINETIC-SVIP Multiplex Settings\n");
PROC_PRINT(" 3 2 1 0\n");
PROC_PRINT(" 10987654321098765432109876543210\n");
PROC_PRINT(" --------------------------------\n");
for (i = 0; i < ARRAY_SIZE(port_clk); i++) {
if (i < 4) {
if (!svip_sys1_clk_is_enabled(port_clk[i]))
continue;
} else {
if (!svip_sys2_clk_is_enabled(port_clk[i]))
continue;
}
PROC_PRINT("P%d.%-10s", i, "DIR:");
for (t = 31; t != -1; t--)
PROC_PRINT("%d", ltq_port_get_dir(i, t) == 1 ? 1 : 0);
PROC_PRINT("\n");
PROC_PRINT("P%d.%-10s", i, "PUEN:");
for (t = 31; t != -1; t--)
PROC_PRINT("%d", ltq_port_get_puden(i, t) == 1 ? 1 : 0);
PROC_PRINT("\n");
PROC_PRINT("P%d.%-10s", i, "ALTSEL0:");
for (t = 31; t != -1; t--)
PROC_PRINT("%d",
ltq_port_get_altsel0(i, t) == 1 ? 1 : 0);
PROC_PRINT("\n");
PROC_PRINT("P%d.%-10s", i, "ALTSEL1:");
for (t = 31; t != -1; t--)
PROC_PRINT("%d",
ltq_port_get_altsel1(i, t) == 1 ? 1 : 0);
PROC_PRINT("\n\n");
}
out:
if (len < 0) {
len = 0;
*eof = 1;
} else if (len < count) {
*eof = 1;
} else {
len = count;
}
*start = buf;
return len;
}
static struct platform_driver ltq_mux_driver = {
.probe = ltq_mux_probe,
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
},
};
int __init ltq_mux_init(void)
{
int ret = platform_driver_register(&ltq_mux_driver);
if (ret) {
printk(KERN_INFO DRV_NAME
": Error registering platform driver!");
return ret;
}
return create_proc_read_entry("driver/ltq_mux", 0, NULL,
ltq_mux_read_procmem, NULL) == NULL;
}
module_init(ltq_mux_init);

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/************************************************************************
*
* Copyright (c) 2007
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/proc_fs.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#include <base_reg.h>
#include <sys1_reg.h>
#include <sys2_reg.h>
#include <lantiq_soc.h>
static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE;
static struct svip_reg_sys2 *const sys2 = (struct svip_reg_sys2 *)LTQ_SYS2_BASE;
void svip_sys1_clk_enable(u32 mask)
{
sys1_w32(sys1_r32(clksr) | mask, clkenr);
asm("sync;");
}
EXPORT_SYMBOL(svip_sys1_clk_enable);
int svip_sys1_clk_is_enabled(u32 mask)
{
return (sys1_r32(clksr) & mask) != 0;
}
EXPORT_SYMBOL(svip_sys1_clk_is_enabled);
void svip_sys2_clk_enable(u32 mask)
{
sys2_w32(sys2_r32(clksr) | mask, clkenr);
asm("sync;");
}
EXPORT_SYMBOL(svip_sys2_clk_enable);
int svip_sys2_clk_is_enabled(u32 mask)
{
return (sys2_r32(clksr) & mask) != 0;
}
EXPORT_SYMBOL(svip_sys2_clk_is_enabled);
int ltq_pms_read_procmem(char *buf, char **start, off_t offset,
int count, int *eof, void *data)
{
long len = 0;
int t = 0;
u32 bit = 0;
u32 reg_tmp, bits_tmp;
len = sprintf(buf, "\nSVIP PMS Settings\n");
len = len + sprintf(buf + len,
" 3 2 1 0\n");
len = len + sprintf(buf + len,
" 210987654321098765432109876543210\n");
len = len + sprintf(buf + len,
"---------------------------------------------\n");
len = len + sprintf(buf + len,
"SYS1_CLKSR: ");
reg_tmp = sys1_r32(clksr);
bit = 0x80000000;
for (t = 31; t != -1; t--) {
bits_tmp = (reg_tmp & bit) >> t;
len = len + sprintf(buf + len, "%d", bits_tmp);
bit = bit >> 1;
}
len = len + sprintf(buf + len, "\n\n");
len = len + sprintf(buf + len, "SYS2_CLKSR: ");
reg_tmp = sys2_r32(clksr);
bit = 0x80000000;
for (t = 31; t != -1; t--) {
bits_tmp = (reg_tmp & bit) >> t;
len = len + sprintf(buf + len, "%d", bits_tmp);
bit = bit >> 1;
}
len = len + sprintf(buf + len, "\n\n");
*eof = 1;
return len;
}
int __init ltq_pms_init_proc(void)
{
return create_proc_read_entry("driver/ltq_pms", 0, NULL,
ltq_pms_read_procmem, NULL) == NULL;
}
module_init(ltq_pms_init_proc);

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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/time.h>
#include <asm/bootinfo.h>
#include <lantiq_soc.h>
#include "../prom.h"
#include "../clk.h"
#include "../machtypes.h"
#include <base_reg.h>
#include <ebu_reg.h>
#define SOC_SVIP "SVIP"
#define PART_SHIFT 12
#define PART_MASK 0x0FFFF000
#define REV_SHIFT 28
#define REV_MASK 0xF0000000
static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE;
void __init ltq_soc_init(void)
{
clkdev_add_static(ltq_svip_cpu_hz(), ltq_svip_fpi_hz(),
ltq_svip_io_region_clock());
}
void __init
ltq_soc_setup(void)
{
if (mips_machtype == LANTIQ_MACH_EASY33016 ||
mips_machtype == LANTIQ_MACH_EASY336) {
ebu_w32(0x120000f1, addr_sel_2);
ebu_w32(LTQ_EBU_CON_0_ADSWP |
LTQ_EBU_CON_0_SETUP |
LTQ_EBU_CON_0_BCGEN_VAL(0x02) |
LTQ_EBU_CON_0_WAITWRC_VAL(7) |
LTQ_EBU_CON_0_WAITRDC_VAL(3) |
LTQ_EBU_CON_0_HOLDC_VAL(3) |
LTQ_EBU_CON_0_RECOVC_VAL(3) |
LTQ_EBU_CON_0_CMULT_VAL(3), con_2);
}
}
void __init
ltq_soc_detect(struct ltq_soc_info *i)
{
i->partnum = (ltq_r32(LTQ_STATUS_CHIPID) & PART_MASK) >> PART_SHIFT;
i->rev = (ltq_r32(LTQ_STATUS_CHIPID) & REV_MASK) >> REV_SHIFT;
sprintf(i->rev_type, "1.%d", i->rev);
switch (i->partnum) {
case SOC_ID_SVIP:
i->name = SOC_SVIP;
i->type = SOC_TYPE_SVIP;
break;
default:
printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum);
while (1);
break;
}
}

95
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <linux/module.h>
#include <asm/reboot.h>
#include <lantiq_soc.h>
#include "../machtypes.h"
#include <base_reg.h>
#include <sys1_reg.h>
#include <boot_reg.h>
#include <ebu_reg.h>
static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE;
static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE;
#define CPLD_CMDREG3 ((volatile unsigned char*)(KSEG1 + 0x120000f3))
extern void switchip_reset(void);
static void ltq_machine_restart(char *command)
{
printk(KERN_NOTICE "System restart\n");
local_irq_disable();
if (mips_machtype == LANTIQ_MACH_EASY33016 ||
mips_machtype == LANTIQ_MACH_EASY336) {
/* We just use the CPLD function to reset the entire system as a
workaround for the switch reset problem */
local_irq_disable();
ebu_w32(0x120000f1, addr_sel_2);
ebu_w32(0x404027ff, con_2);
if (mips_machtype == LANTIQ_MACH_EASY336)
/* set bit 0 to reset SVIP */
*CPLD_CMDREG3 = (1<<0);
else
/* set bit 7 to reset SVIP, set bit 3 to reset xT */
*CPLD_CMDREG3 = (1<<7) | (1<<3);
} else {
*LTQ_BOOT_RVEC(0) = 0;
/* reset all except PER, SUBSYS and CPU0 */
sys1_w32(0x00043F3E, rreqr);
/* release WDT0 reset */
sys1_w32(0x00000100, rrlsr);
/* restore reset value for clock enables */
sys1_w32(~0x0c000040, clkclr);
/* reset SUBSYS (incl. DDR2) and CPU0 */
sys1_w32(0x00030001, rbtr);
}
for (;;)
;
}
static void ltq_machine_halt(void)
{
printk(KERN_NOTICE "System halted.\n");
local_irq_disable();
for (;;)
;
}
static void ltq_machine_power_off(void)
{
printk(KERN_NOTICE "Please turn off the power now.\n");
local_irq_disable();
for (;;)
;
}
/* This function is used by the watchdog driver */
int ltq_reset_cause(void)
{
return 0;
}
EXPORT_SYMBOL_GPL(ltq_reset_cause);
static int __init mips_reboot_setup(void)
{
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
pm_power_off = ltq_machine_power_off;
return 0;
}
arch_initcall(mips_reboot_setup);

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/******************************************************************************
Copyright (c) 2007, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
******************************************************************************
Module : switchip_setup.c
Date : 2007-11-09
Description : Basic setup of embedded ethernet switch "SwitchIP"
Remarks: andreas.schmidt@infineon.com
*****************************************************************************/
/* TODO: get rid of #ifdef CONFIG_LANTIQ_MACH_EASY336 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/time.h>
#include <base_reg.h>
#include <es_reg.h>
#include <sys1_reg.h>
#include <dma_reg.h>
#include <lantiq_soc.h>
static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE;
static struct svip_reg_es *const es = (struct svip_reg_es *)LTQ_ES_BASE;
/* PHY Organizationally Unique Identifier (OUI) */
#define PHY_OUI_PMC 0x00E004
#define PHY_OUI_VITESSE 0x008083
#define PHY_OUI_DEFAULT 0xFFFFFF
unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr);
void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr,
unsigned short data);
static int phy_address[2] = {0, 1};
static u32 phy_oui;
static void switchip_mdio_poll_init(void);
static void _switchip_mdio_poll(struct work_struct *work);
/* struct workqueue_struct mdio_poll_task; */
static struct workqueue_struct *mdio_poll_workqueue;
DECLARE_DELAYED_WORK(mdio_poll_work, _switchip_mdio_poll);
static int old_link_status[2] = {-1, -1};
/**
* Autonegotiation check.
* This funtion checks for link changes. If a link change has occured it will
* update certain switch registers.
*/
static void _switchip_check_phy_status(int port)
{
int new_link_status;
unsigned short reg1;
reg1 = switchip_phy_read(phy_address[port], 1);
if ((reg1 == 0xFFFF) || (reg1 == 0x0000))
return; /* no PHY connected */
new_link_status = reg1 & 4;
if (old_link_status[port] ^ new_link_status) {
/* link status change */
if (!new_link_status) {
if (port == 0)
es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p0_ctl);
else
es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p1_ctl);
/* read again; link bit is latched low! */
reg1 = switchip_phy_read(phy_address[port], 1);
new_link_status = reg1 & 4;
}
if (new_link_status) {
unsigned short reg0, reg4, reg5, reg9, reg10;
int phy_pause, phy_speed, phy_duplex;
int aneg_enable, aneg_cmpt;
reg0 = switchip_phy_read(phy_address[port], 0);
reg4 = switchip_phy_read(phy_address[port], 4);
aneg_enable = reg0 & 0x1000;
aneg_cmpt = reg1 & 0x20;
if (aneg_enable && aneg_cmpt) {
reg5 = switchip_phy_read(phy_address[port], 5);
switch (phy_oui) {
#ifdef CONFIG_LANTIQ_MACH_EASY336
case PHY_OUI_PMC:
/* PMC Sierra supports 1Gigabit FD,
* only. On successful
* auto-negotiation, we are sure this
* is what the LP can. */
phy_pause = ((reg4 & reg5) & 0x0080) >> 7;
phy_speed = 2;
phy_duplex = 1;
break;
#endif
case PHY_OUI_VITESSE:
case PHY_OUI_DEFAULT:
reg9 = switchip_phy_read(phy_address[port], 9);
reg10 = switchip_phy_read(phy_address[port], 10);
/* Check if advertise and partner
* agree on pause */
phy_pause = ((reg4 & reg5) & 0x0400) >> 10;
/* Find the best mode both partners
* support
* Priority: 1GB-FD, 1GB-HD, 100MB-FD,
* 100MB-HD, 10MB-FD, 10MB-HD */
phy_speed = ((((reg9<<2) & reg10)
& 0x0c00) >> 6) |
(((reg4 & reg5) & 0x01e0) >> 5);
if (phy_speed >= 0x0020) {
phy_speed = 2;
phy_duplex = 1;
} else if (phy_speed >= 0x0010) {
phy_speed = 2;
phy_duplex = 0;
} else if (phy_speed >= 0x0008) {
phy_speed = 1;
phy_duplex = 1;
} else if (phy_speed >= 0x0004) {
phy_speed = 1;
phy_duplex = 0;
} else if (phy_speed >= 0x0002) {
phy_speed = 0;
phy_duplex = 1;
} else {
phy_speed = 0;
phy_duplex = 0;
}
break;
default:
phy_pause = (reg4 & 0x0400) >> 10;
phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1);
phy_duplex = (reg0 >> 8)&1;
break;
}
} else {
/* parallel detection or fixed speed */
phy_pause = (reg4 & 0x0400) >> 10;
phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1);
phy_duplex = (reg0 >> 8)&1;
}
if (port == 0) {
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0SPD,
LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(phy_speed),
rgmii_ctl);
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0DUP,
LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(phy_duplex),
rgmii_ctl);
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0FCE,
LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause),
rgmii_ctl);
es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl);
} else {
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1SPD,
LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(phy_speed),
rgmii_ctl);
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1DUP,
LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(phy_duplex),
rgmii_ctl);
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1FCE,
LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause),
rgmii_ctl);
es_w32_mask(1, LTQ_ES_P0_CTL_REG_FLP, p1_ctl);
}
}
}
old_link_status[port] = new_link_status;
}
static void _switchip_mdio_poll(struct work_struct *work)
{
if (es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) {
_switchip_check_phy_status(0);
_switchip_check_phy_status(1);
}
queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2);
}
static void switchip_mdio_poll_init(void)
{
mdio_poll_workqueue = create_workqueue("SVIP MDIP poll");
INIT_DELAYED_WORK(&mdio_poll_work, _switchip_mdio_poll);
queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2);
}
unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr)
{
/* TODO: protect MDIO access with semaphore */
es_w32(LTQ_ES_MDIO_CTL_REG_MBUSY
| LTQ_ES_MDIO_CTL_REG_OP_VAL(2) /* read operation */
| LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr)
| LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl);
while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY);
return es_r32(mdio_data) & 0xFFFF;
}
EXPORT_SYMBOL(switchip_phy_read);
void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr,
unsigned short data)
{
/* TODO: protect MDIO access with semaphore */
es_w32(LTQ_ES_MDIO_CTL_REG_WD_VAL(data)
| LTQ_ES_MDIO_CTL_REG_MBUSY
| LTQ_ES_MDIO_CTL_REG_OP_VAL(1) /* write operation */
| LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr)
| LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl);
while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY);
return;
}
EXPORT_SYMBOL(switchip_phy_write);
const static u32 switch_reset_offset_000[] = {
/*b8000000:*/ 0xffffffff, 0x00000001, 0x00000001, 0x00000003,
/*b8000010:*/ 0x04070001, 0x04070001, 0x04070001, 0xffffffff,
/*b8000020:*/ 0x00001be8, 0x00001be8, 0x00001be8, 0xffffffff,
/*b8000030:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001,
/*b8000040:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001,
/*b8000050:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001,
/*b8000060:*/ 0x00000000, 0x00000000, 0x00081000, 0x001f7777,
/*b8000070:*/ 0x00000000, 0x00000000, 0x0c00ac2b, 0x0000fa50,
/*b8000080:*/ 0x00001000, 0x00001800, 0x00000000, 0x00000000,
/*b8000090:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b80000a0:*/ 0x00000000, 0x00000050, 0x00000010, 0x00000000,
/*b80000b0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b80000c0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b80000d0:*/ 0xffffffff, 0x00000000, 0x00000000
};
const static u32 switch_reset_offset_100[] = {
/*b8000100:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000110:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000120:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000130:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000140:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000150:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000160:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000170:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000180:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b8000190:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b80001a0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/*b80001b0:*/ 0x00000000, 0x00000000
};
/*
* Switch Reset.
*/
void switchip_reset(void)
{
volatile unsigned int *reg;
volatile unsigned int rdreg;
int i;
sys1_w32(SYS1_CLKENR_ETHSW, clkenr);
asm("sync");
/* disable P0 */
es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p0_ctl);
/* disable P1 */
es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p1_ctl);
/* disable P2 */
es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p2_ctl);
/**************************************
* BEGIN: Procedure to clear MAC table
**************************************/
for (i = 0; i < 3; i++) {
int result;
/* check if access engine is available */
while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY);
/* initialise to first address */
es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(3)
| LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(0), adr_tb_ctl2);
/* wait while busy */
while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY);
/* setup the portmap */
es_w32_mask(0, LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1 << i),
adr_tb_ctl1);
do {
/* search for addresses by port */
es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(2)
| LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(9), adr_tb_ctl2);
/* wait while busy */
while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY);
result = LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(es_r32(adr_tb_st2));
if (result == 0x101) {
printk(KERN_ERR "%s, cmd error\n", __func__);
return;
}
/* if Command OK, address found... */
if (result == 0) {
unsigned char mac[6];
mac[5] = (es_r32(adr_tb_st0) >> 0) & 0xff;
mac[4] = (es_r32(adr_tb_st0) >> 8) & 0xff;
mac[3] = (es_r32(adr_tb_st0) >> 16) & 0xff;
mac[2] = (es_r32(adr_tb_st0) >> 24) & 0xff;
mac[1] = (es_r32(adr_tb_st1) >> 0) & 0xff;
mac[0] = (es_r32(adr_tb_st1) >> 8) & 0xff;
/* setup address */
es_w32((mac[5] << 0) |
(mac[4] << 8) |
(mac[3] << 16) |
(mac[2] << 24), adr_tb_ctl0);
es_w32(LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1<<i) |
LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(0) |
(mac[0] << 8) |
(mac[1] << 0), adr_tb_ctl1);
/* erase address */
es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(1) |
LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(15),
adr_tb_ctl2);
/* wait, while busy */
while (es_r32(adr_tb_st2) &
LTQ_ES_ADR_TB_ST2_REG_BUSY);
}
} while (result == 0);
}
/**************************************
* END: Procedure to clear MAC table
**************************************/
/* reset RMON counters */
es_w32(LTQ_ES_RMON_CTL_REG_BAS | LTQ_ES_RMON_CTL_REG_CAC_VAL(3),
rmon_ctl);
/* bring all registers to reset state */
reg = LTQ_ES_PS_REG;
for (i = 0; i < ARRAY_SIZE(switch_reset_offset_000); i++) {
if ((reg == LTQ_ES_PS_REG) ||
(reg >= LTQ_ES_ADR_TB_CTL0_REG &&
reg <= LTQ_ES_ADR_TB_ST2_REG))
continue;
if (switch_reset_offset_000[i] != 0xFFFFFFFF) {
/* write reset value to register */
*reg = switch_reset_offset_000[i];
/* read register value back */
rdreg = *reg;
if (reg == LTQ_ES_SW_GCTL1_REG)
rdreg &= ~LTQ_ES_SW_GCTL1_REG_BISTDN;
/* compare read value with written one */
if (rdreg != switch_reset_offset_000[i]) {
printk(KERN_ERR "%s,%d: reg %08x mismatch "
"[has:%08x, expect:%08x]\n",
__func__, __LINE__,
(unsigned int)reg, rdreg,
switch_reset_offset_000[i]);
}
}
reg++;
}
reg = LTQ_ES_VLAN_FLT0_REG;
for (i = 0; i < ARRAY_SIZE(switch_reset_offset_100); i++) {
*reg = switch_reset_offset_100[i];
rdreg = *reg;
if (rdreg != switch_reset_offset_100[i]) {
printk(KERN_ERR "%s,%d: reg %08x mismatch "
"[has:%08x, expect:%08x]\n", __func__, __LINE__,
(unsigned int)reg, rdreg,
switch_reset_offset_100[i]);
}
reg++;
}
}
EXPORT_SYMBOL(switchip_reset);
static u32 get_phy_oui(unsigned char phy_addr)
{
u32 oui;
int i, bit, byte, shift, w;
u16 reg_id[2];
/* read PHY identifier registers 1 and 2 */
reg_id[0] = switchip_phy_read(phy_addr, 2);
reg_id[1] = switchip_phy_read(phy_addr, 3);
oui = 0;
w = 1;
shift = 7;
byte = 1;
for (i = 0, bit = 10; i <= 21; i++, bit++) {
oui |= ((reg_id[w] & (1<<bit)) ? 1 : 0) << shift;
if (!(shift % 8)) {
byte++;
if (byte == 2)
shift = 15;
else
shift = 21;
} else {
shift--;
}
if (w == 1 && bit == 15) {
bit = -1;
w = 0;
}
}
return oui;
}
/*
* Switch Initialization.
*/
int switchip_init(void)
{
int eth_port, phy_present = 0;
u16 reg, mode;
sys1_w32(SYS1_CLKENR_ETHSW, clkenr);
asm("sync");
/* Enable Switch, if not already done so */
if ((es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) == 0)
es_w32_mask(0, LTQ_ES_SW_GCTL0_REG_SE, sw_gctl0);
/* Wait for completion of MBIST */
while (LTQ_ES_SW_GCTL1_REG_BISTDN_GET(es_r32(sw_gctl1)) == 0);
switchip_reset();
mode = LTQ_ES_RGMII_CTL_REG_IS_GET(es_r32(rgmii_ctl));
eth_port = (mode == 2 ? 1 : 0);
/* Set the primary port(port toward backplane) as sniffer port,
changing from P2 which is the reset setting */
es_w32_mask(LTQ_ES_SW_GCTL0_REG_SNIFFPN,
LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(eth_port),
sw_gctl0);
/* Point MDIO state machine to invalid PHY addresses 8 and 9 */
es_w32_mask(0, LTQ_ES_SW_GCTL0_REG_PHYBA, sw_gctl0);
/* Add CRC for packets from DMA to PMAC.
Remove CRC for packets from PMAC to DMA. */
es_w32(LTQ_ES_PMAC_HD_CTL_RC | LTQ_ES_PMAC_HD_CTL_AC, pmac_hd_ctl);
phy_oui = get_phy_oui(0);
switch (phy_oui) {
#ifdef CONFIG_LANTIQ_MACH_EASY336
case PHY_OUI_PMC:
phy_address[0] = (mode == 2 ? -1 : 2);
phy_address[1] = (mode == 2 ? 2 : -1);
break;
#endif
case PHY_OUI_VITESSE:
default:
phy_oui = PHY_OUI_DEFAULT;
phy_address[0] = (mode == 2 ? 1 : 0);
phy_address[1] = (mode == 2 ? 0 : 1);
break;
}
/****** PORT 0 *****/
reg = switchip_phy_read(phy_address[0], 1);
if ((reg != 0x0000) && (reg != 0xffff)) {
/* PHY connected? */
phy_present |= 1;
/* Set Rx- and TxDelay in case of RGMII */
switch (mode) {
case 0: /* *RGMII,RGMII */
case 2: /* RGMII,*GMII */
/* program clock delay in PHY, not in SVIP */
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0RDLY, 0, rgmii_ctl);
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0TDLY, 0, rgmii_ctl);
if (phy_oui == PHY_OUI_VITESSE ||
phy_oui == PHY_OUI_DEFAULT) {
switchip_phy_write(phy_address[0], 31, 0x0001);
switchip_phy_write(phy_address[0], 28, 0xA000);
switchip_phy_write(phy_address[0], 31, 0x0000);
}
default:
break;
}
if (phy_oui == PHY_OUI_VITESSE ||
phy_oui == PHY_OUI_DEFAULT) {
/* Program PHY advertisements and
* restart auto-negotiation */
switchip_phy_write(phy_address[0], 4, 0x05E1);
switchip_phy_write(phy_address[0], 9, 0x0300);
switchip_phy_write(phy_address[0], 0, 0x3300);
} else {
reg = switchip_phy_read(phy_address[1], 0);
reg |= 0x1000; /* auto-negotiation enable */
switchip_phy_write(phy_address[1], 0, reg);
reg |= 0x0200; /* auto-negotiation restart */
switchip_phy_write(phy_address[1], 0, reg);
}
} else {
/* Force SWITCH link with highest capability:
* 100M FD for MII
* 1G FD for GMII/RGMII
*/
switch (mode) {
case 1: /* *MII,MII */
case 3: /* *MII,RGMII */
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(1),
rgmii_ctl);
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(1),
rgmii_ctl);
break;
case 0: /* *RGMII,RGMII */
case 2: /* RGMII,*GMII */
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(2),
rgmii_ctl);
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(1),
rgmii_ctl);
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0RDLY, 0, rgmii_ctl);
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(2),
rgmii_ctl);
break;
}
es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl);
}
/****** PORT 1 *****/
reg = switchip_phy_read(phy_address[1], 1);
if ((reg != 0x0000) && (reg != 0xffff)) {
/* PHY connected? */
phy_present |= 2;
/* Set Rx- and TxDelay in case of RGMII */
switch (mode) {
case 0: /* *RGMII,RGMII */
case 3: /* *MII,RGMII */
/* program clock delay in PHY, not in SVIP */
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1RDLY, 0, rgmii_ctl);
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1TDLY, 0, rgmii_ctl);
if (phy_oui == PHY_OUI_VITESSE ||
phy_oui == PHY_OUI_DEFAULT) {
switchip_phy_write(phy_address[1], 31, 0x0001);
switchip_phy_write(phy_address[1], 28, 0xA000);
switchip_phy_write(phy_address[1], 31, 0x0000);
}
break;
case 2: /* RGMII,*GMII */
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2),
rgmii_ctl);
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl);
#ifdef CONFIG_LANTIQ_MACH_EASY336
if (phy_oui == PHY_OUI_PMC) {
switchip_phy_write(phy_address[1], 24, 0x0510);
switchip_phy_write(phy_address[1], 17, 0xA38C);
switchip_phy_write(phy_address[1], 17, 0xA384);
}
#endif
break;
default:
break;
}
/* Program PHY advertisements and restart auto-negotiation */
if (phy_oui == PHY_OUI_VITESSE ||
phy_oui == PHY_OUI_DEFAULT) {
switchip_phy_write(phy_address[1], 4, 0x05E1);
switchip_phy_write(phy_address[1], 9, 0x0300);
switchip_phy_write(phy_address[1], 0, 0x3300);
} else {
reg = switchip_phy_read(phy_address[1], 0);
reg |= 0x1000; /* auto-negotiation enable */
switchip_phy_write(phy_address[1], 0, reg);
reg |= 0x0200; /* auto-negotiation restart */
switchip_phy_write(phy_address[1], 0, reg);
}
} else {
/* Force SWITCH link with highest capability:
* 100M FD for MII
* 1G FD for GMII/RGMII
*/
switch (mode) {
case 1: /* *MII,MII */
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(1),
rgmii_ctl);
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl);
break;
case 0: /* *RGMII,RGMII */
case 3: /* *MII,RGMII */
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2),
rgmii_ctl);
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl);
es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1RDLY, 0, rgmii_ctl);
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(2),
rgmii_ctl);
break;
case 2: /* RGMII,*GMII */
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2),
rgmii_ctl);
es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl);
break;
}
es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl);
}
/*
* Allow unknown unicast/multicast and broadcasts
* on all ports.
*/
es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_UP_VAL(7), sw_gctl1);
es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_BP_VAL(7), sw_gctl1);
es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_MP_VAL(7), sw_gctl1);
es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_RP_VAL(7), sw_gctl1);
/* Enable LAN port(s) */
if (eth_port == 0)
es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p0_ctl);
else
es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p1_ctl);
/* Enable CPU Port (Forwarding State) */
es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p2_ctl);
if (phy_present)
switchip_mdio_poll_init();
return 0;
}
EXPORT_SYMBOL(switchip_init);
device_initcall(switchip_init);

329
target/linux/lantiq/files/arch/mips/lantiq/xway/clk.c Normal file
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@ -0,0 +1,329 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/io.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <asm/time.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include <lantiq_soc.h>
#include "../clk.h"
static unsigned int ltq_ram_clocks[] = {
CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
#define BASIC_FREQUENCY_1 35328000
#define BASIC_FREQUENCY_2 36000000
#define BASIS_REQUENCY_USB 12000000
#define GET_BITS(x, msb, lsb) \
(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
/* legacy xway clock */
#define LTQ_CGU_PLL0_CFG 0x0004
#define LTQ_CGU_PLL1_CFG 0x0008
#define LTQ_CGU_PLL2_CFG 0x000C
#define LTQ_CGU_SYS 0x0010
#define LTQ_CGU_UPDATE 0x0014
#define LTQ_CGU_IF_CLK 0x0018
#define LTQ_CGU_OSC_CON 0x001C
#define LTQ_CGU_SMD 0x0020
#define LTQ_CGU_CT1SR 0x0028
#define LTQ_CGU_CT2SR 0x002C
#define LTQ_CGU_PCMCR 0x0030
#define LTQ_CGU_PCI_CR 0x0034
#define LTQ_CGU_PD_PC 0x0038
#define LTQ_CGU_FMR 0x003C
#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
#define CGU_PLL0_BYPASS \
(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
#define CGU_PLL0_CFG_DSMSEL \
(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
#define CGU_PLL0_CFG_FRAC_EN \
(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
#define CGU_PLL1_SRC \
(ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
(ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
#define CGU_SYS_FPI_SEL (1 << 6)
#define CGU_SYS_DDR_SEL 0x3
#define CGU_PLL0_SRC (1 << 29)
#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
/* vr9 clock */
#define LTQ_CGU_SYS_VR9 0x0c
#define LTQ_CGU_IF_CLK_VR9 0x24
static unsigned int ltq_get_pll0_fdiv(void);
static inline unsigned int get_input_clock(int pll)
{
switch (pll) {
case 0:
if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
return BASIS_REQUENCY_USB;
else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
return BASIC_FREQUENCY_1;
else
return BASIC_FREQUENCY_2;
case 1:
if (CGU_PLL1_SRC)
return BASIS_REQUENCY_USB;
else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
return BASIC_FREQUENCY_1;
else
return BASIC_FREQUENCY_2;
case 2:
switch (CGU_PLL2_SRC) {
case 0:
return ltq_get_pll0_fdiv();
case 1:
return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
BASIC_FREQUENCY_1 :
BASIC_FREQUENCY_2;
case 2:
return BASIS_REQUENCY_USB;
}
default:
return 0;
}
}
static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
{
u64 res, clock = get_input_clock(pll);
res = num * clock;
do_div(res, den);
return res;
}
static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
unsigned int K)
{
unsigned int num = ((N + 1) << 10) + K;
unsigned int den = (M + 1) << 10;
return cal_dsm(pll, num, den);
}
static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
unsigned int K)
{
unsigned int num = ((N + 1) << 11) + K + 512;
unsigned int den = (M + 1) << 11;
return cal_dsm(pll, num, den);
}
static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
unsigned int K)
{
unsigned int num = K >= 512 ?
((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
unsigned int den = (M + 1) << 12;
return cal_dsm(pll, num, den);
}
static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
{
if (!dsmsel)
return mash_dsm(pll, M, N, K);
else if (!phase_div_en)
return mash_dsm(pll, M, N, K);
else
return ssff_dsm_2(pll, M, N, K);
}
static inline unsigned int ltq_get_pll0_fosc(void)
{
if (CGU_PLL0_BYPASS)
return get_input_clock(0);
else
return !CGU_PLL0_CFG_FRAC_EN
? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
CGU_PLL0_CFG_DSMSEL,
CGU_PLL0_PHASE_DIVIDER_ENABLE)
: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
CGU_PLL0_PHASE_DIVIDER_ENABLE);
}
static unsigned int ltq_get_pll0_fdiv(void)
{
unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
return (ltq_get_pll0_fosc() + (div >> 1)) / div;
}
unsigned long ltq_danube_io_region_clock(void)
{
unsigned int ret = ltq_get_pll0_fosc();
switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0x3) {
default:
case 0:
return (ret + 1) / 2;
case 1:
return (ret * 2 + 2) / 5;
case 2:
return (ret + 1) / 3;
case 3:
return (ret + 2) / 4;
}
}
unsigned long ltq_danube_fpi_bus_clock(int fpi)
{
unsigned long ret = ltq_danube_io_region_clock();
if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
ret >>= 1;
return ret;
}
unsigned long ltq_danube_fpi_hz(void)
{
unsigned long ddr_clock = DDR_HZ;
if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
return ddr_clock >> 1;
return ddr_clock;
}
unsigned long ltq_danube_cpu_hz(void)
{
switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
case 0:
return CLOCK_333M;
case 4:
return DDR_HZ;
case 8:
return DDR_HZ << 1;
default:
return DDR_HZ >> 1;
}
}
unsigned long ltq_ar9_sys_hz(void)
{
if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2)
return CLOCK_393M;
return CLOCK_333M;
}
unsigned long ltq_ar9_fpi_hz(void)
{
unsigned long sys = ltq_ar9_sys_hz();
if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0))
return sys;
return sys >> 1;
}
unsigned long ltq_ar9_cpu_hz(void)
{
if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2))
return ltq_ar9_fpi_hz();
else
return ltq_ar9_sys_hz();
}
unsigned long ltq_vr9_cpu_hz(void)
{
unsigned int cpu_sel;
unsigned long clk;
cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
switch (cpu_sel) {
case 0:
clk = CLOCK_600M;
break;
case 1:
clk = CLOCK_500M;
break;
case 2:
clk = CLOCK_393M;
break;
case 3:
clk = CLOCK_333M;
break;
case 5:
case 6:
clk = CLOCK_196_608M;
break;
case 7:
clk = CLOCK_167M;
break;
case 4:
case 8:
case 9:
clk = CLOCK_125M;
break;
default:
clk = 0;
break;
}
return clk;
}
unsigned long ltq_vr9_fpi_hz(void)
{
unsigned int ocp_sel, cpu_clk;
unsigned long clk;
cpu_clk = ltq_vr9_cpu_hz();
ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3;
switch (ocp_sel) {
case 0:
/* OCP ratio 1 */
clk = cpu_clk;
break;
case 2:
/* OCP ratio 2 */
clk = cpu_clk / 2;
break;
case 3:
/* OCP ratio 2.5 */
clk = (cpu_clk * 2) / 5;
break;
case 4:
/* OCP ratio 3 */
clk = cpu_clk / 3;
break;
default:
clk = 0;
break;
}
return clk;
}
unsigned long ltq_vr9_fpi_bus_clock(int fpi)
{
return ltq_vr9_fpi_hz();
}

45
target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/mtd/physmap.h>
#include <linux/kernel.h>
#include <linux/reboot.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/etherdevice.h>
#include <linux/reboot.h>
#include <linux/time.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <lantiq_soc.h>
#include <lantiq_irq.h>
#include <lantiq_platform.h>
static u64 dmamask = (u32)0x1fffffff;
static struct platform_device platform_dev = {
.name = "ifxusb_hcd",
.dev.dma_mask = &dmamask,
};
int __init
xway_register_hcd(int *pins)
{
platform_dev.dev.platform_data = pins;
return platform_device_register(&platform_dev);
}

17
target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.h Normal file
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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
*/
#ifndef _LTQ_DEV_HCD_H__
#define _LTQ_DEV_HCD_H__
#include <lantiq_platform.h>
extern void __init xway_register_hcd(int *pin);
#endif

176
target/linux/lantiq/files/arch/mips/lantiq/xway/gptu.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <linux/export.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <asm/reboot.h>
#include <lantiq_soc.h>
#include "../clk.h"
#include "../devices.h"
#define ltq_gptu_w32(x, y) ltq_w32((x), ltq_gptu_membase + (y))
#define ltq_gptu_r32(x) ltq_r32(ltq_gptu_membase + (x))
/* the magic ID byte of the core */
#define GPTU_MAGIC 0x59
/* clock control register */
#define GPTU_CLC 0x00
/* id register */
#define GPTU_ID 0x08
/* interrupt node enable */
#define GPTU_IRNEN 0xf4
/* interrupt control register */
#define GPTU_IRCR 0xf8
/* interrupt capture register */
#define GPTU_IRNCR 0xfc
/* there are 3 identical blocks of 2 timers. calculate register offsets */
#define GPTU_SHIFT(x) (x % 2 ? 4 : 0)
#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10)
/* timer control register */
#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
/* timer auto reload register */
#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
/* timer manual reload register */
#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
/* timer count register */
#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
/* GPTU_CON(x) */
#define CON_CNT BIT(2)
#define CON_EDGE_FALL BIT(7)
#define CON_SYNC BIT(8)
#define CON_CLK_INT BIT(10)
/* GPTU_RUN(x) */
#define RUN_SEN BIT(0)
#define RUN_RL BIT(2)
/* set clock to runmode */
#define CLC_RMC BIT(8)
/* bring core out of suspend */
#define CLC_SUSPEND BIT(4)
/* the disable bit */
#define CLC_DISABLE BIT(0)
#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
enum gptu_timer {
TIMER1A = 0,
TIMER1B,
TIMER2A,
TIMER2B,
TIMER3A,
TIMER3B
};
static struct resource ltq_gptu_resource =
MEM_RES("GPTU", LTQ_GPTU_BASE_ADDR, LTQ_GPTU_SIZE);
static void __iomem *ltq_gptu_membase;
static irqreturn_t timer_irq_handler(int irq, void *priv)
{
int timer = irq - TIMER_INTERRUPT;
ltq_gptu_w32(1 << timer, GPTU_IRNCR);
return IRQ_HANDLED;
}
static void gptu_hwinit(void)
{
struct clk *clk = clk_get_sys("ltq_gptu", NULL);
clk_enable(clk);
ltq_gptu_w32(0x00, GPTU_IRNEN);
ltq_gptu_w32(0xff, GPTU_IRNCR);
ltq_gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
}
static void gptu_hwexit(void)
{
ltq_gptu_w32(0x00, GPTU_IRNEN);
ltq_gptu_w32(0xff, GPTU_IRNCR);
ltq_gptu_w32(CLC_DISABLE, GPTU_CLC);
}
static int ltq_gptu_enable(struct clk *clk)
{
int ret = request_irq(TIMER_INTERRUPT + clk->bits, timer_irq_handler,
IRQF_TIMER, "timer", NULL);
if (ret) {
pr_err("gptu: failed to request irq\n");
return ret;
}
ltq_gptu_w32(CON_CNT | CON_EDGE_FALL | CON_SYNC | CON_CLK_INT,
GPTU_CON(clk->bits));
ltq_gptu_w32(1, GPTU_RLD(clk->bits));
ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) | clk->bits, GPTU_IRNEN);
ltq_gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
return 0;
}
static void ltq_gptu_disable(struct clk *clk)
{
ltq_gptu_w32(0, GPTU_RUN(clk->bits));
ltq_gptu_w32(0, GPTU_CON(clk->bits));
ltq_gptu_w32(0, GPTU_RLD(clk->bits));
ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) & ~clk->bits, GPTU_IRNEN);
free_irq(TIMER_INTERRUPT + clk->bits, NULL);
}
static inline void clkdev_add_gptu(const char *con, unsigned int timer)
{
struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
clk->cl.dev_id = "ltq_gptu";
clk->cl.con_id = con;
clk->cl.clk = clk;
clk->enable = ltq_gptu_enable;
clk->disable = ltq_gptu_disable;
clk->bits = timer;
clkdev_add(&clk->cl);
}
static int __init gptu_setup(void)
{
/* remap gptu register range */
ltq_gptu_membase = ltq_remap_resource(&ltq_gptu_resource);
if (!ltq_gptu_membase)
panic("Failed to remap gptu memory");
/* power up the core */
gptu_hwinit();
/* the gptu has a ID register */
if (((ltq_gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
pr_err("gptu: failed to find magic\n");
gptu_hwexit();
return -ENAVAIL;
}
/* register the clocks */
clkdev_add_gptu("timer1a", TIMER1A);
clkdev_add_gptu("timer1b", TIMER1B);
clkdev_add_gptu("timer2a", TIMER2A);
clkdev_add_gptu("timer2b", TIMER2B);
clkdev_add_gptu("timer3a", TIMER3A);
clkdev_add_gptu("timer3b", TIMER3B);
pr_info("gptu: 6 timers loaded\n");
return 0;
}
arch_initcall(gptu_setup);

58
target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50601.c
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <lantiq.h>
#include "../machtypes.h"
#include "devices.h"
static struct mtd_partition easy50601_partitions[] = {
{
.name = "uboot",
.offset = 0x0,
.size = 0x10000,
},
{
.name = "uboot_env",
.offset = 0x10000,
.size = 0x10000,
},
{
.name = "linux",
.offset = 0x20000,
.size = 0x3d0000,
},
};
static struct physmap_flash_data easy50601_flash_data = {
.nr_parts = ARRAY_SIZE(easy50601_partitions),
.parts = easy50601_partitions,
};
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = -1, /* use EPHY */
};
static void __init
easy50601_init(void)
{
ltq_register_nor(&easy50601_flash_data);
ltq_register_etop(&ltq_eth_data);
}
MIPS_MACHINE(LTQ_MACH_EASY50601,
"EASY50601",
"EASY50601 Eval Board",
easy50601_init);

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target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50712.c
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/phy.h>
#include <lantiq_soc.h>
#include <irq.h>
#include "../machtypes.h"
#include "devices.h"
static struct mtd_partition easy50712_partitions[] = {
{
.name = "uboot",
.offset = 0x0,
.size = 0x10000,
},
{
.name = "uboot_env",
.offset = 0x10000,
.size = 0x10000,
},
{
.name = "linux",
.offset = 0x20000,
.size = 0x3d0000,
},
};
static struct physmap_flash_data easy50712_flash_data = {
.nr_parts = ARRAY_SIZE(easy50712_partitions),
.parts = easy50712_partitions,
};
static struct ltq_pci_data ltq_pci_data = {
.clock = PCI_CLOCK_INT,
.gpio = PCI_GNT1 | PCI_REQ1,
.irq = {
[14] = INT_NUM_IM0_IRL0 + 22,
},
};
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_MII,
};
static void __init
easy50712_init(void)
{
ltq_register_gpio_stp();
ltq_register_nor(&easy50712_flash_data);
ltq_register_pci(&ltq_pci_data);
ltq_register_etop(&ltq_eth_data);
ltq_register_tapi();
}
MIPS_MACHINE(LTQ_MACH_EASY50712,
"EASY50712",
"EASY50712 Eval Board",
easy50712_init);

216
target/linux/lantiq/files/arch/mips/lantiq/xway/nand.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <lantiq_soc.h>
#include <lantiq_irq.h>
#include <lantiq_platform.h>
#include "devices.h"
/* nand registers */
#define LTQ_EBU_NAND_WAIT 0xB4
#define LTQ_EBU_NAND_ECC0 0xB8
#define LTQ_EBU_NAND_ECC_AC 0xBC
#define LTQ_EBU_NAND_CON 0xB0
#define LTQ_EBU_ADDSEL1 0x24
/* gpio definitions */
#define PIN_ALE 13
#define PIN_CLE 24
#define PIN_CS1 23
#define PIN_RDY 48 /* NFLASH_READY */
#define PIN_RD 49 /* NFLASH_READ_N */
#define NAND_CMD_ALE (1 << 2)
#define NAND_CMD_CLE (1 << 3)
#define NAND_CMD_CS (1 << 4)
#define NAND_WRITE_CMD_RESET 0xff
#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
#define NAND_WRITE_DATA (NAND_CMD_CS)
#define NAND_READ_DATA (NAND_CMD_CS)
#define NAND_WAIT_WR_C (1 << 3)
#define NAND_WAIT_RD (0x1)
#define ADDSEL1_MASK(x) (x << 4)
#define ADDSEL1_REGEN 1
#define BUSCON1_SETUP (1 << 22)
#define BUSCON1_BCGEN_RES (0x3 << 12)
#define BUSCON1_WAITWRC2 (2 << 8)
#define BUSCON1_WAITRDC2 (2 << 6)
#define BUSCON1_HOLDC1 (1 << 4)
#define BUSCON1_RECOVC1 (1 << 2)
#define BUSCON1_CMULT4 1
#define NAND_CON_NANDM 1
#define NAND_CON_CSMUX (1 << 1)
#define NAND_CON_CS_P (1 << 4)
#define NAND_CON_SE_P (1 << 5)
#define NAND_CON_WP_P (1 << 6)
#define NAND_CON_PRE_P (1 << 7)
#define NAND_CON_IN_CS0 0
#define NAND_CON_OUT_CS0 0
#define NAND_CON_IN_CS1 (1 << 8)
#define NAND_CON_OUT_CS1 (1 << 10)
#define NAND_CON_CE (1 << 20)
#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000)
static const char *part_probes[] = { "cmdlinepart", NULL };
static void xway_select_chip(struct mtd_info *mtd, int chip)
{
switch (chip) {
case -1:
ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON);
ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON);
break;
case 0:
ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON);
ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON);
/* reset the nand chip */
while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
ltq_w32(NAND_WRITE_CMD_RESET,
((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
break;
default:
BUG();
}
}
static void xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_CLE)
this->IO_ADDR_W = (void __iomem *)
(NAND_BASE_ADDRESS | NAND_WRITE_CMD);
else if (ctrl & NAND_ALE)
this->IO_ADDR_W = (void __iomem *)
(NAND_BASE_ADDRESS | NAND_WRITE_ADDR);
}
if (data != NAND_CMD_NONE) {
*(volatile u8*) ((u32) this->IO_ADDR_W) = data;
while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
}
}
static int xway_dev_ready(struct mtd_info *mtd)
{
return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD;
}
void nand_write(unsigned int addr, unsigned int val)
{
ltq_w32(val, ((u32 *) (NAND_BASE_ADDRESS | addr)));
while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
}
unsigned char xway_read_byte(struct mtd_info *mtd)
{
return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
}
static void xway_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
int i;
for (i = 0; i < len; i++)
{
unsigned char res8 = ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
buf[i] = res8;
}
}
static void xway_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
int i;
for (i = 0; i < len; i++)
{
ltq_w8(buf[i], ((u32*)(NAND_BASE_ADDRESS | (NAND_WRITE_DATA))));
while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
}
}
int xway_probe(struct platform_device *pdev)
{
/* might need this later ?
ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1");
*/
ltq_gpio_request(&pdev->dev, PIN_CLE, 2, 1, "NAND_CLE");
ltq_gpio_request(&pdev->dev, PIN_ALE, 2, 1, "NAND_ALE");
if (ltq_is_ar9() || ltq_is_vr9()) {
ltq_gpio_request(&pdev->dev, PIN_RDY, 2, 0, "NAND_BSY");
ltq_gpio_request(&pdev->dev, PIN_RD, 2, 1, "NAND_RD");
}
ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
| ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
| NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
ltq_w32(NAND_WRITE_CMD_RESET,
((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
return 0;
}
static struct platform_nand_data falcon_flash_nand_data = {
.chip = {
.nr_chips = 1,
.chip_delay = 30,
.part_probe_types = part_probes,
},
.ctrl = {
.probe = xway_probe,
.cmd_ctrl = xway_cmd_ctrl,
.dev_ready = xway_dev_ready,
.select_chip = xway_select_chip,
.read_byte = xway_read_byte,
.read_buf = xway_read_buf,
.write_buf = xway_write_buf,
}
};
static struct resource ltq_nand_res =
MEM_RES("nand", 0x14000000, 0x7ffffff);
static struct platform_device ltq_flash_nand = {
.name = "gen_nand",
.id = -1,
.num_resources = 1,
.resource = &ltq_nand_res,
.dev = {
.platform_data = &falcon_flash_nand_data,
},
};
void __init xway_register_nand(struct mtd_partition *parts, int count)
{
falcon_flash_nand_data.chip.partitions = parts;
falcon_flash_nand_data.chip.nr_partitions = count;
platform_device_register(&ltq_flash_nand);
}

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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/export.h>
#include <linux/clk.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <lantiq_soc.h>
#include "../prom.h"
#include "devices.h"
#define SOC_DANUBE "Danube"
#define SOC_TWINPASS "Twinpass"
#define SOC_AMAZON_SE "Amazon_SE"
#define SOC_AR9 "AR9"
#define SOC_GR9 "GR9"
#define SOC_VR9 "VR9"
#define PART_SHIFT 12
#define PART_MASK 0x0FFFFFFF
#define REV_SHIFT 28
#define REV_MASK 0xF0000000
void __init ltq_soc_detect(struct ltq_soc_info *i)
{
i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
sprintf(i->rev_type, "1.%d", i->rev);
switch (i->partnum) {
case SOC_ID_DANUBE1:
case SOC_ID_DANUBE2:
i->name = SOC_DANUBE;
i->type = SOC_TYPE_DANUBE;
break;
case SOC_ID_TWINPASS:
i->name = SOC_TWINPASS;
i->type = SOC_TYPE_DANUBE;
break;
case SOC_ID_ARX188:
case SOC_ID_ARX168_1:
case SOC_ID_ARX168_2:
case SOC_ID_ARX182:
i->name = SOC_AR9;
i->type = SOC_TYPE_AR9;
break;
case SOC_ID_GRX188:
case SOC_ID_GRX168:
i->name = SOC_GR9;
i->type = SOC_TYPE_AR9;
break;
case SOC_ID_AMAZON_SE_1:
case SOC_ID_AMAZON_SE_2:
i->name = SOC_AMAZON_SE;
i->type = SOC_TYPE_AMAZON_SE;
#ifdef CONFIG_PCI
panic("ase is only supported for non pci kernels");
#endif
break;
case SOC_ID_VRX282:
case SOC_ID_VRX268:
case SOC_ID_VRX288:
i->name = SOC_VR9;
i->type = SOC_TYPE_VR9_1;
break;
case SOC_ID_GRX268:
case SOC_ID_GRX288:
i->name = SOC_GR9;
i->type = SOC_TYPE_VR9_1;
break;
case SOC_ID_VRX268_2:
case SOC_ID_VRX288_2:
i->name = SOC_VR9;
i->type = SOC_TYPE_VR9_2;
break;
case SOC_ID_GRX282_2:
case SOC_ID_GRX288_2:
i->name = SOC_GR9;
i->type = SOC_TYPE_VR9_2;
default:
unreachable();
break;
}
}
void __init ltq_soc_setup(void)
{
if (ltq_is_ase())
ltq_register_ase_asc();
else
ltq_register_asc(1);
ltq_register_gpio();
ltq_register_wdt();
}

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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#include <linux/ioport.h>
#include <linux/export.h>
#include <linux/clkdev.h>
#include <lantiq_soc.h>
#include "../clk.h"
#include "../devices.h"
/* clock control register */
#define CGU_IFCCR 0x0018
/* system clock register */
#define CGU_SYS 0x0010
/* pci control register */
#define CGU_PCICR 0x0034
/* ephy configuration register */
#define CGU_EPHY 0x10
/* power control register */
#define PMU_PWDCR 0x1C
/* power status register */
#define PMU_PWDSR 0x20
/* power control register */
#define PMU_PWDCR1 0x24
/* power status register */
#define PMU_PWDSR1 0x28
/* power control register */
#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
/* power status register */
#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
/* PMU - power management unit */
#define PMU_USB0_P BIT(0)
#define PMU_PCI BIT(4)
#define PMU_DMA BIT(5)
#define PMU_USB0 BIT(6)
#define PMU_EPHY BIT(7) /* ase */
#define PMU_SPI BIT(8)
#define PMU_DFE BIT(9)
#define PMU_EBU BIT(10)
#define PMU_STP BIT(11)
#define PMU_GPT BIT(12)
#define PMU_PPE BIT(13)
#define PMU_AHBS BIT(13) /* vr9 */
#define PMU_FPI BIT(14)
#define PMU_AHBM BIT(15)
#define PMU_PPE_QSB BIT(18)
#define PMU_PPE_SLL01 BIT(19)
#define PMU_PPE_TC BIT(21)
#define PMU_PPE_EMA BIT(22)
#define PMU_PPE_DPLUM BIT(23)
#define PMU_PPE_DPLUS BIT(24)
#define PMU_USB1_P BIT(26)
#define PMU_USB1 BIT(27)
#define PMU_SWITCH BIT(28)
#define PMU_PPE_TOP BIT(29)
#define PMU_GPHY BIT(30)
#define PMU_PCIE_CLK BIT(31)
#define PMU1_PCIE_PHY BIT(0)
#define PMU1_PCIE_CTL BIT(1)
#define PMU1_PCIE_PDI BIT(4)
#define PMU1_PCIE_MSI BIT(5)
#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
static struct resource ltq_cgu_resource =
MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE);
static struct resource ltq_pmu_resource =
MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE);
static struct resource ltq_ebu_resource =
MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
void __iomem *ltq_cgu_membase;
void __iomem *ltq_ebu_membase;
static void __iomem *ltq_pmu_membase;
static int ltq_cgu_enable(struct clk *clk)
{
ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
return 0;
}
static void ltq_cgu_disable(struct clk *clk)
{
ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
}
static int ltq_pmu_enable(struct clk *clk)
{
int err = 1000000;
ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits,
PWDCR(clk->module));
do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits));
if (!err)
panic("activating PMU module failed!\n");
return 0;
}
static void ltq_pmu_disable(struct clk *clk)
{
ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) | clk->bits,
PWDCR(clk->module));
}
static int ltq_pci_enable(struct clk *clk)
{
unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
/* set clock bus speed */
if (ltq_is_ar9()) {
ifccr &= ~0x1f00000;
if (clk->rate == CLOCK_33M)
ifccr |= 0xe00000;
else
ifccr |= 0x700000; /* 62.5M */
} else {
ifccr &= ~0xf00000;
if (clk->rate == CLOCK_33M)
ifccr |= 0x800000;
else
ifccr |= 0x400000; /* 62.5M */
}
ltq_cgu_w32(ifccr, CGU_IFCCR);
return 0;
}
static int ltq_pci_ext_enable(struct clk *clk)
{
/* enable external pci clock */
ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
CGU_IFCCR);
ltq_cgu_w32((1 << 30), CGU_PCICR);
return 0;
}
static void ltq_pci_ext_disable(struct clk *clk)
{
/* disable external pci clock (internal) */
ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
CGU_IFCCR);
ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
}
/* manage the clock gates via PMU */
static inline void clkdev_add_pmu(const char *dev, const char *con,
unsigned int module, unsigned int bits)
{
struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
clk->cl.dev_id = dev;
clk->cl.con_id = con;
clk->cl.clk = clk;
clk->enable = ltq_pmu_enable;
clk->disable = ltq_pmu_disable;
clk->module = module;
clk->bits = bits;
clkdev_add(&clk->cl);
}
/* manage the clock generator */
static inline void clkdev_add_cgu(const char *dev, const char *con,
unsigned int bits)
{
struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
clk->cl.dev_id = dev;
clk->cl.con_id = con;
clk->cl.clk = clk;
clk->enable = ltq_cgu_enable;
clk->disable = ltq_cgu_disable;
clk->bits = bits;
clkdev_add(&clk->cl);
}
/* pci needs its own enable function */
static inline void clkdev_add_pci(void)
{
struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
/* main pci clock */
clk->cl.dev_id = "ltq_pci";
clk->cl.con_id = NULL;
clk->cl.clk = clk;
clk->rate = CLOCK_33M;
clk->enable = ltq_pci_enable;
clk->disable = ltq_pmu_disable;
clk->module = 0;
clk->bits = PMU_PCI;
clkdev_add(&clk->cl);
/* use internal/external bus clock */
clk_ext->cl.dev_id = "ltq_pci";
clk_ext->cl.con_id = "external";
clk_ext->cl.clk = clk_ext;
clk_ext->enable = ltq_pci_ext_enable;
clk_ext->disable = ltq_pci_ext_disable;
clkdev_add(&clk_ext->cl);
}
void __init ltq_soc_init(void)
{
ltq_pmu_membase = ltq_remap_resource(&ltq_pmu_resource);
if (!ltq_pmu_membase)
panic("Failed to remap pmu memory\n");
ltq_cgu_membase = ltq_remap_resource(&ltq_cgu_resource);
if (!ltq_cgu_membase)
panic("Failed to remap cgu memory\n");
ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_resource);
if (!ltq_ebu_membase)
panic("Failed to remap ebu memory\n");
/* make sure to unprotect the memory region where flash is located */
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
/* add our clocks */
clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI);
clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
clkdev_add_pmu("ltq_spi.0", NULL, 0, PMU_SPI);
clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT);
clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU);
if (!ltq_is_vr9())
clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
if (!ltq_is_ase())
clkdev_add_pci();
if (ltq_is_ase()) {
if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
else
clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
clkdev_add_pmu("ltq_dsl", NULL, 0,
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_AHBS | PMU_DFE);
} else if (ltq_is_vr9()) {
clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
ltq_vr9_fpi_hz());
clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
clkdev_add_pmu("usb0", NULL, 0, PMU_USB0 | PMU_USB0_P);
clkdev_add_pmu("usb1", NULL, 0, PMU_USB1 | PMU_USB1_P);
clkdev_add_pmu("ltq_vrx200", NULL, 0,
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB);
clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS);
} else if (ltq_is_ar9()) {
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
ltq_ar9_fpi_hz());
clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
clkdev_add_pmu("ltq_dsl", NULL, 0,
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
} else {
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
ltq_danube_io_region_clock());
clkdev_add_pmu("ltq_dsl", NULL, 0,
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
}
}

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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/types.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/init.h>
#include <linux/uaccess.h>
#include <linux/unistd.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include "../clk.h"
#include <lantiq_soc.h>
#include <lantiq_irq.h>
#include <lantiq_timer.h>
#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
#ifdef TIMER1A
#define FIRST_TIMER TIMER1A
#else
#define FIRST_TIMER 2
#endif
/*
* GPTC divider is set or not.
*/
#define GPTU_CLC_RMC_IS_SET 0
/*
* Timer Interrupt (IRQ)
*/
/* Must be adjusted when ICU driver is available */
#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
/*
* Bits Operation
*/
#define GET_BITS(x, msb, lsb) \
(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
#define SET_BITS(x, msb, lsb, value) \
(((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
(((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
/*
* GPTU Register Mapping
*/
#define LQ_GPTU (KSEG1 + 0x1E100A00)
#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
/*
* Clock Control Register
*/
#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
/*
* ID Register
*/
#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
/*
* Control Register of Timer/Counter nX
* n is the index of block (1 based index)
* X is either A or B
*/
#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
#define TIMER_FLAG_NONE_EDGE 0x0000
#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
#define TIMER_FLAG_REAL 0x0000
#define TIMER_FLAG_INVERT 0x0040
#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
struct timer_dev_timer {
unsigned int f_irq_on;
unsigned int irq;
unsigned int flag;
unsigned long arg1;
unsigned long arg2;
};
struct timer_dev {
struct mutex gptu_mutex;
unsigned int number_of_timers;
unsigned int occupation;
unsigned int f_gptu_on;
struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
};
unsigned long ltq_danube_fpi_bus_clock(int fpi);
unsigned long ltq_vr9_fpi_bus_clock(int fpi);
unsigned int ltq_get_fpi_bus_clock(int fpi) {
if (ltq_is_ase())
return CLOCK_133M;
else if (ltq_is_vr9())
return ltq_vr9_fpi_bus_clock(fpi);
return ltq_danube_fpi_bus_clock(fpi);
}
static long gptu_ioctl(struct file *, unsigned int, unsigned long);
static int gptu_open(struct inode *, struct file *);
static int gptu_release(struct inode *, struct file *);
static struct file_operations gptu_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = gptu_ioctl,
.open = gptu_open,
.release = gptu_release
};
static struct miscdevice gptu_miscdev = {
.minor = MISC_DYNAMIC_MINOR,
.name = "gptu",
.fops = &gptu_fops,
};
static struct timer_dev timer_dev;
static irqreturn_t timer_irq_handler(int irq, void *p)
{
unsigned int timer;
unsigned int flag;
struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
timer = irq - TIMER_INTERRUPT;
if (timer < timer_dev.number_of_timers
&& dev_timer == &timer_dev.timer[timer]) {
/* Clear interrupt. */
ltq_w32(1 << timer, LQ_GPTU_IRNCR);
/* Call user hanler or signal. */
flag = dev_timer->flag;
if (!(timer & 0x01)
|| TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
/* 16-bit timer or timer A of 32-bit timer */
switch (TIMER_FLAG_MASK_HANDLE(flag)) {
case TIMER_FLAG_CALLBACK_IN_IRQ:
case TIMER_FLAG_CALLBACK_IN_HB:
if (dev_timer->arg1)
(*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
break;
case TIMER_FLAG_SIGNAL:
send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
break;
}
}
}
return IRQ_HANDLED;
}
static inline void lq_enable_gptu(void)
{
struct clk *clk = clk_get_sys("ltq_gptu", NULL);
clk_enable(clk);
//ltq_pmu_enable(PMU_GPT);
/* Set divider as 1, disable write protection for SPEN, enable module. */
*LQ_GPTU_CLC =
GPTU_CLC_SMC_SET(0x00) |
GPTU_CLC_RMC_SET(0x01) |
GPTU_CLC_FSOE_SET(0) |
GPTU_CLC_SBWE_SET(1) |
GPTU_CLC_EDIS_SET(0) |
GPTU_CLC_SPEN_SET(0) |
GPTU_CLC_DISR_SET(0);
}
static inline void lq_disable_gptu(void)
{
struct clk *clk = clk_get_sys("ltq_gptu", NULL);
ltq_w32(0x00, LQ_GPTU_IRNEN);
ltq_w32(0xfff, LQ_GPTU_IRNCR);
/* Set divider as 0, enable write protection for SPEN, disable module. */
*LQ_GPTU_CLC =
GPTU_CLC_SMC_SET(0x00) |
GPTU_CLC_RMC_SET(0x00) |
GPTU_CLC_FSOE_SET(0) |
GPTU_CLC_SBWE_SET(0) |
GPTU_CLC_EDIS_SET(0) |
GPTU_CLC_SPEN_SET(0) |
GPTU_CLC_DISR_SET(1);
clk_enable(clk);
}
int lq_request_timer(unsigned int timer, unsigned int flag,
unsigned long value, unsigned long arg1, unsigned long arg2)
{
int ret = 0;
unsigned int con_reg, irnen_reg;
int n, X;
if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
timer, flag, value);
if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
value &= 0xFFFF;
else
timer &= ~0x01;
mutex_lock(&timer_dev.gptu_mutex);
/*
* Allocate timer.
*/
if (timer < FIRST_TIMER) {
unsigned int mask;
unsigned int shift;
/* This takes care of TIMER1B which is the only choice for Voice TAPI system */
unsigned int offset = TIMER2A;
/*
* Pick up a free timer.
*/
if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
mask = 1 << offset;
shift = 1;
} else {
mask = 3 << offset;
shift = 2;
}
for (timer = offset;
timer < offset + timer_dev.number_of_timers;
timer += shift, mask <<= shift)
if (!(timer_dev.occupation & mask)) {
timer_dev.occupation |= mask;
break;
}
if (timer >= offset + timer_dev.number_of_timers) {
printk("failed![%d]\n", __LINE__);
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
} else
ret = timer;
} else {
register unsigned int mask;
/*
* Check if the requested timer is free.
*/
mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
if ((timer_dev.occupation & mask)) {
printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
__LINE__, mask, timer_dev.occupation);
mutex_unlock(&timer_dev.gptu_mutex);
return -EBUSY;
} else {
timer_dev.occupation |= mask;
ret = 0;
}
}
/*
* Prepare control register value.
*/
switch (TIMER_FLAG_MASK_EDGE(flag)) {
default:
case TIMER_FLAG_NONE_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x00);
break;
case TIMER_FLAG_RISE_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x01);
break;
case TIMER_FLAG_FALL_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x02);
break;
case TIMER_FLAG_ANY_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x03);
break;
}
if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
con_reg |=
TIMER_FLAG_MASK_SRC(flag) ==
TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
GPTU_CON_SRC_EXT_SET(0);
else
con_reg |=
TIMER_FLAG_MASK_SRC(flag) ==
TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
GPTU_CON_SRC_EG_SET(0);
con_reg |=
TIMER_FLAG_MASK_SYNC(flag) ==
TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
GPTU_CON_SYNC_SET(1);
con_reg |=
TIMER_FLAG_MASK_INVERT(flag) ==
TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
con_reg |=
TIMER_FLAG_MASK_SIZE(flag) ==
TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
GPTU_CON_EXT_SET(1);
con_reg |=
TIMER_FLAG_MASK_STOP(flag) ==
TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
con_reg |=
TIMER_FLAG_MASK_TYPE(flag) ==
TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
GPTU_CON_CNT_SET(1);
con_reg |=
TIMER_FLAG_MASK_DIR(flag) ==
TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
/*
* Fill up running data.
*/
timer_dev.timer[timer - FIRST_TIMER].flag = flag;
timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
/*
* Enable GPTU module.
*/
if (!timer_dev.f_gptu_on) {
lq_enable_gptu();
timer_dev.f_gptu_on = 1;
}
/*
* Enable IRQ.
*/
if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
timer_dev.timer[timer - FIRST_TIMER].arg1 =
(unsigned long) find_task_by_vpid((int) arg1);
irnen_reg = 1 << (timer - FIRST_TIMER);
if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
|| (TIMER_FLAG_MASK_HANDLE(flag) ==
TIMER_FLAG_CALLBACK_IN_IRQ
&& timer_dev.timer[timer - FIRST_TIMER].arg1)) {
enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
}
} else
irnen_reg = 0;
/*
* Write config register, reload value and enable interrupt.
*/
n = timer >> 1;
X = timer & 0x01;
*LQ_GPTU_CON(n, X) = con_reg;
*LQ_GPTU_RELOAD(n, X) = value;
/* printk("reload value = %d\n", (u32)value); */
*LQ_GPTU_IRNEN |= irnen_reg;
mutex_unlock(&timer_dev.gptu_mutex);
printk("successful!\n");
return ret;
}
EXPORT_SYMBOL(lq_request_timer);
int lq_free_timer(unsigned int timer)
{
unsigned int flag;
unsigned int mask;
int n, X;
if (!timer_dev.f_gptu_on)
return -EINVAL;
if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
flag = timer_dev.timer[timer - FIRST_TIMER].flag;
if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
n = timer >> 1;
X = timer & 0x01;
if (GPTU_CON_EN(n, X))
*LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
*LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
*LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
}
timer_dev.occupation &= ~mask;
if (!timer_dev.occupation && timer_dev.f_gptu_on) {
lq_disable_gptu();
timer_dev.f_gptu_on = 0;
}
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
EXPORT_SYMBOL(lq_free_timer);
int lq_start_timer(unsigned int timer, int is_resume)
{
unsigned int flag;
unsigned int mask;
int n, X;
if (!timer_dev.f_gptu_on)
return -EINVAL;
if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
flag = timer_dev.timer[timer - FIRST_TIMER].flag;
if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
mask = (TIMER_FLAG_MASK_SIZE(flag) ==
TIMER_FLAG_16BIT ? 1 : 3) << timer;
if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
n = timer >> 1;
X = timer & 0x01;
*LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
EXPORT_SYMBOL(lq_start_timer);
int lq_stop_timer(unsigned int timer)
{
unsigned int flag;
unsigned int mask;
int n, X;
if (!timer_dev.f_gptu_on)
return -EINVAL;
if (timer < FIRST_TIMER
|| timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
flag = timer_dev.timer[timer - FIRST_TIMER].flag;
if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
n = timer >> 1;
X = timer & 0x01;
*LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
EXPORT_SYMBOL(lq_stop_timer);
int lq_reset_counter_flags(u32 timer, u32 flags)
{
unsigned int oflag;
unsigned int mask, con_reg;
int n, X;
if (!timer_dev.f_gptu_on)
return -EINVAL;
if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
switch (TIMER_FLAG_MASK_EDGE(flags)) {
default:
case TIMER_FLAG_NONE_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x00);
break;
case TIMER_FLAG_RISE_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x01);
break;
case TIMER_FLAG_FALL_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x02);
break;
case TIMER_FLAG_ANY_EDGE:
con_reg = GPTU_CON_EDGE_SET(0x03);
break;
}
if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
else
con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
timer_dev.timer[timer - FIRST_TIMER].flag = flags;
if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
n = timer >> 1;
X = timer & 0x01;
*LQ_GPTU_CON(n, X) = con_reg;
smp_wmb();
printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
EXPORT_SYMBOL(lq_reset_counter_flags);
int lq_get_count_value(unsigned int timer, unsigned long *value)
{
unsigned int flag;
unsigned int mask;
int n, X;
if (!timer_dev.f_gptu_on)
return -EINVAL;
if (timer < FIRST_TIMER
|| timer >= FIRST_TIMER + timer_dev.number_of_timers)
return -EINVAL;
mutex_lock(&timer_dev.gptu_mutex);
flag = timer_dev.timer[timer - FIRST_TIMER].flag;
if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
timer &= ~0x01;
mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
if (((timer_dev.occupation & mask) ^ mask)) {
mutex_unlock(&timer_dev.gptu_mutex);
return -EINVAL;
}
n = timer >> 1;
X = timer & 0x01;
*value = *LQ_GPTU_COUNT(n, X);
mutex_unlock(&timer_dev.gptu_mutex);
return 0;
}
EXPORT_SYMBOL(lq_get_count_value);
u32 lq_cal_divider(unsigned long freq)
{
u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
u32 clock_divider = 1;
module_freq = fpi * 1000;
do_div(module_freq, clock_divider * freq);
return module_freq;
}
EXPORT_SYMBOL(lq_cal_divider);
int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
int is_ext_src, unsigned int handle_flag, unsigned long arg1,
unsigned long arg2)
{
unsigned long divider;
unsigned int flag;
divider = lq_cal_divider(freq);
if (divider == 0)
return -EINVAL;
flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
| (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
| (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
| TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
| TIMER_FLAG_MASK_HANDLE(handle_flag);
printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
timer, freq, divider);
return lq_request_timer(timer, flag, divider, arg1, arg2);
}
EXPORT_SYMBOL(lq_set_timer);
int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
unsigned long arg1, unsigned long arg2)
{
printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
return lq_request_timer(timer, flag, reload, arg1, arg2);
}
EXPORT_SYMBOL(lq_set_counter);
static long gptu_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int ret;
struct gptu_ioctl_param param;
if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
return -EFAULT;
copy_from_user(&param, (void *) arg, sizeof(param));
if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
|| GPTU_SET_COUNTER) && param.timer < 2)
|| cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
&& !access_ok(VERIFY_WRITE, arg,
sizeof(struct gptu_ioctl_param)))
return -EFAULT;
switch (cmd) {
case GPTU_REQUEST_TIMER:
ret = lq_request_timer(param.timer, param.flag, param.value,
(unsigned long) param.pid,
(unsigned long) param.sig);
if (ret > 0) {
copy_to_user(&((struct gptu_ioctl_param *) arg)->
timer, &ret, sizeof(&ret));
ret = 0;
}
break;
case GPTU_FREE_TIMER:
ret = lq_free_timer(param.timer);
break;
case GPTU_START_TIMER:
ret = lq_start_timer(param.timer, param.flag);
break;
case GPTU_STOP_TIMER:
ret = lq_stop_timer(param.timer);
break;
case GPTU_GET_COUNT_VALUE:
ret = lq_get_count_value(param.timer, &param.value);
if (!ret)
copy_to_user(&((struct gptu_ioctl_param *) arg)->
value, &param.value,
sizeof(param.value));
break;
case GPTU_CALCULATE_DIVIDER:
param.value = lq_cal_divider(param.value);
if (param.value == 0)
ret = -EINVAL;
else {
copy_to_user(&((struct gptu_ioctl_param *) arg)->
value, &param.value,
sizeof(param.value));
ret = 0;
}
break;
case GPTU_SET_TIMER:
ret = lq_set_timer(param.timer, param.value,
TIMER_FLAG_MASK_STOP(param.flag) !=
TIMER_FLAG_ONCE ? 1 : 0,
TIMER_FLAG_MASK_SRC(param.flag) ==
TIMER_FLAG_EXT_SRC ? 1 : 0,
TIMER_FLAG_MASK_HANDLE(param.flag) ==
TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
TIMER_FLAG_NO_HANDLE,
(unsigned long) param.pid,
(unsigned long) param.sig);
if (ret > 0) {
copy_to_user(&((struct gptu_ioctl_param *) arg)->
timer, &ret, sizeof(&ret));
ret = 0;
}
break;
case GPTU_SET_COUNTER:
lq_set_counter(param.timer, param.flag, param.value, 0, 0);
if (ret > 0) {
copy_to_user(&((struct gptu_ioctl_param *) arg)->
timer, &ret, sizeof(&ret));
ret = 0;
}
break;
default:
ret = -ENOTTY;
}
return ret;
}
static int gptu_open(struct inode *inode, struct file *file)
{
return 0;
}
static int gptu_release(struct inode *inode, struct file *file)
{
return 0;
}
int __init lq_gptu_init(void)
{
int ret;
unsigned int i;
ltq_w32(0, LQ_GPTU_IRNEN);
ltq_w32(0xfff, LQ_GPTU_IRNCR);
memset(&timer_dev, 0, sizeof(timer_dev));
mutex_init(&timer_dev.gptu_mutex);
lq_enable_gptu();
timer_dev.number_of_timers = GPTU_ID_CFG * 2;
lq_disable_gptu();
if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
ret = misc_register(&gptu_miscdev);
if (ret) {
printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
return ret;
} else {
printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
}
for (i = 0; i < timer_dev.number_of_timers; i++) {
ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
if (ret) {
for (; i >= 0; i--)
free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
misc_deregister(&gptu_miscdev);
printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
return ret;
} else {
timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
disable_irq(timer_dev.timer[i].irq);
printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
}
}
return 0;
}
void __exit lq_gptu_exit(void)
{
unsigned int i;
for (i = 0; i < timer_dev.number_of_timers; i++) {
if (timer_dev.timer[i].f_irq_on)
disable_irq(timer_dev.timer[i].irq);
free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
}
lq_disable_gptu();
misc_deregister(&gptu_miscdev);
}
module_init(lq_gptu_init);
module_exit(lq_gptu_exit);

81
target/linux/lantiq/files/arch/mips/pci/fixup-lantiq-pcie.c Normal file
View File

@ -0,0 +1,81 @@
/******************************************************************************
**
** FILE NAME : ifxmips_fixup_pcie.c
** PROJECT : IFX UEIP for VRX200
** MODULES : PCIe
**
** DATE : 02 Mar 2009
** AUTHOR : Lei Chuanhua
** DESCRIPTION : PCIe Root Complex Driver
** COPYRIGHT : Copyright (c) 2009
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
** HISTORY
** $Version $Date $Author $Comment
** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version
*******************************************************************************/
/*!
\file ifxmips_fixup_pcie.c
\ingroup IFX_PCIE
\brief PCIe Fixup functions source file
*/
#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/pci_ids.h>
#include <lantiq_soc.h>
#include "pcie-lantiq.h"
#define PCI_VENDOR_ID_INFINEON 0x15D1
#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F
#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011
#define PCI_VENDOR_ID_LANTIQ 0x1BEF
#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011
static void __devinit
ifx_pcie_fixup_resource(struct pci_dev *dev)
{
u32 reg;
IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev));
IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s: fixup host controller %s (%04x:%04x)\n",
__func__, pci_name(dev), dev->vendor, dev->device);
/* Setup COMMAND register */
reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* |
PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR;
pci_write_config_word(dev, PCI_COMMAND, reg);
IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev));
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource);
static void __devinit
ifx_pcie_rc_class_early_fixup(struct pci_dev *dev)
{
IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev));
if (dev->devfn == PCI_DEVFN(0, 0) &&
(dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff);
printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__);
}
IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev));
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE,
ifx_pcie_rc_class_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE,
ifx_pcie_rc_class_early_fixup);

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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
*/
#include <linux/of_irq.h>
#include <linux/of_pci.h>
int (*ltqpci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin) = NULL;
int (*ltqpci_plat_arch_init)(struct pci_dev *dev) = NULL;
int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
int *ltq_pci_irq_map;
int pcibios_plat_dev_init(struct pci_dev *dev)
{
if (ltqpci_plat_arch_init)
return ltqpci_plat_arch_init(dev);
if (ltqpci_plat_dev_init)
return ltqpci_plat_dev_init(dev);
return 0;
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (ltqpci_map_irq)
return ltqpci_map_irq(dev, slot, pin);
if (ltq_pci_irq_map[slot]) {
dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, ltq_pci_irq_map[slot]);
return ltq_pci_irq_map[slot];
}
printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
slot);
return 0;
}

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/******************************************************************************
**
** FILE NAME : ifxmips_pcie_msi.c
** PROJECT : IFX UEIP for VRX200
** MODULES : PCI MSI sub module
**
** DATE : 02 Mar 2009
** AUTHOR : Lei Chuanhua
** DESCRIPTION : PCIe MSI Driver
** COPYRIGHT : Copyright (c) 2009
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
** HISTORY
** $Date $Author $Comment
** 02 Mar,2009 Lei Chuanhua Initial version
*******************************************************************************/
/*!
\defgroup IFX_PCIE_MSI MSI OS APIs
\ingroup IFX_PCIE
\brief PCIe bus driver OS interface functions
*/
/*!
\file ifxmips_pcie_msi.c
\ingroup IFX_PCIE
\brief PCIe MSI OS interface file
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/module.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include "pcie-lantiq.h"
#define IFX_MSI_IRQ_NUM 16
#define SM(_v, _f) (((_v) << _f##_S) & (_f))
#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000)
#define IFX_PCIE_MSI_IR0 (INT_NUM_IM4_IRL0 + 27)
#define IFX_PCIE_MSI_IR1 (INT_NUM_IM4_IRL0 + 28)
#define IFX_PCIE_MSI_IR2 (INT_NUM_IM4_IRL0 + 29)
#define IFX_PCIE_MSI_IR3 (INT_NUM_IM0_IRL0 + 30)
#define IFX_MSI_PCI_INT_DISABLE 0x80000000
#define IFX_MSI_PIC_INT_LINE 0x30000000
#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000
#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF
#define IFX_MSI_PIC_BIG_ENDIAN 1
#define IFX_MSI_PIC_INT_LINE_S 28
#define IFX_MSI_PIC_MSG_ADDR_S 16
#define IFX_MSI_PIC_MSG_DATA_S 0x0
enum {
IFX_PCIE_MSI_IDX0 = 0,
IFX_PCIE_MSI_IDX1,
IFX_PCIE_MSI_IDX2,
IFX_PCIE_MSI_IDX3,
};
typedef struct ifx_msi_irq_idx {
const int irq;
const int idx;
}ifx_msi_irq_idx_t;
struct ifx_msi_pic {
volatile u32 pic_table[IFX_MSI_IRQ_NUM];
volatile u32 pic_endian; /* 0x40 */
};
typedef struct ifx_msi_pic *ifx_msi_pic_t;
typedef struct ifx_msi_irq {
const volatile ifx_msi_pic_t msi_pic_p;
const u32 msi_phy_base;
const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM];
/*
* Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
* in use.
*/
u16 msi_free_irq_bitmask;
/*
* Each bit in msi_multiple_irq_bitmask tells that the device using
* this bit in msi_free_irq_bitmask is also using the next bit. This
* is used so we can disable all of the MSI interrupts when a device
* uses multiple.
*/
u16 msi_multiple_irq_bitmask;
}ifx_msi_irq_t;
static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = {
{
.msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE,
.msi_phy_base = PCIE_MSI_PHY_BASE,
.msi_irq_idx = {
{IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
{IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
{IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
{IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
{IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
{IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
{IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
{IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
},
.msi_free_irq_bitmask = 0,
.msi_multiple_irq_bitmask= 0,
},
#ifdef CONFIG_IFX_PCIE_2ND_CORE
{
.msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE,
.msi_phy_base = PCIE1_MSI_PHY_BASE,
.msi_irq_idx = {
{IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
{IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
{IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
{IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
{IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
{IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
{IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
{IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
},
.msi_free_irq_bitmask = 0,
.msi_multiple_irq_bitmask= 0,
},
#endif /* CONFIG_IFX_PCIE_2ND_CORE */
};
/*
* This lock controls updates to msi_free_irq_bitmask,
* msi_multiple_irq_bitmask and pic register settting
*/
static DEFINE_SPINLOCK(ifx_pcie_msi_lock);
void pcie_msi_pic_init(int pcie_port)
{
spin_lock(&ifx_pcie_msi_lock);
msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN;
spin_unlock(&ifx_pcie_msi_lock);
}
/**
* \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
* \brief Called when a driver request MSI interrupts instead of the
* legacy INT A-D. This routine will allocate multiple interrupts
* for MSI devices that support them. A device can override this by
* programming the MSI control bits [6:4] before calling
* pci_enable_msi().
*
* \param[in] pdev Device requesting MSI interrupts
* \param[in] desc MSI descriptor
*
* \return -EINVAL Invalid pcie root port or invalid msi bit
* \return 0 OK
* \ingroup IFX_PCIE_MSI
*/
int
arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
int irq, pos;
u16 control;
int irq_idx;
int irq_step;
int configured_private_bits;
int request_private_bits;
struct msi_msg msg;
u16 search_mask;
struct ifx_pci_controller *ctrl = pdev->bus->sysdata;
int pcie_port = ctrl->port;
IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev));
/* XXX, skip RC MSI itself */
if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__);
return -EINVAL;
}
/*
* Read the MSI config to figure out how many IRQs this device
* wants. Most devices only want 1, which will give
* configured_private_bits and request_private_bits equal 0.
*/
pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control);
/*
* If the number of private bits has been configured then use
* that value instead of the requested number. This gives the
* driver the chance to override the number of interrupts
* before calling pci_enable_msi().
*/
configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
if (configured_private_bits == 0) {
/* Nothing is configured, so use the hardware requested size */
request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
}
else {
/*
* Use the number of configured bits, assuming the
* driver wanted to override the hardware request
* value.
*/
request_private_bits = configured_private_bits;
}
/*
* The PCI 2.3 spec mandates that there are at most 32
* interrupts. If this device asks for more, only give it one.
*/
if (request_private_bits > 5) {
request_private_bits = 0;
}
again:
/*
* The IRQs have to be aligned on a power of two based on the
* number being requested.
*/
irq_step = (1 << request_private_bits);
/* Mask with one bit for each IRQ */
search_mask = (1 << irq_step) - 1;
/*
* We're going to search msi_free_irq_bitmask_lock for zero
* bits. This represents an MSI interrupt number that isn't in
* use.
*/
spin_lock(&ifx_pcie_msi_lock);
for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) {
if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) {
msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos;
msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos;
break;
}
}
spin_unlock(&ifx_pcie_msi_lock);
/* Make sure the search for available interrupts didn't fail */
if (pos >= IFX_MSI_IRQ_NUM) {
if (request_private_bits) {
IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free "
"interrupts, trying just one", __func__, 1 << request_private_bits);
request_private_bits = 0;
goto again;
}
else {
printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__);
return -EINVAL;
}
}
irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq;
irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx;
IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx);
/*
* Initialize MSI. This has to match the memory-write endianess from the device
* Address bits [23:12]
*/
spin_lock(&ifx_pcie_msi_lock);
msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) |
SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) |
SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
/* Enable this entry */
msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE;
spin_unlock(&ifx_pcie_msi_lock);
IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n",
pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]);
/* Update the number of IRQs the device has available to it */
control &= ~PCI_MSI_FLAGS_QSIZE;
control |= (request_private_bits << 4);
pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control);
irq_set_msi_desc(irq, desc);
msg.address_hi = 0x0;
msg.address_lo = msi_irqs[pcie_port].msi_phy_base;
msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data);
write_msi_msg(irq, &msg);
IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
return 0;
}
static int
pcie_msi_irq_to_port(unsigned int irq, int *port)
{
int ret = 0;
if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 ||
irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) {
*port = IFX_PCIE_PORT0;
}
#ifdef CONFIG_IFX_PCIE_2ND_CORE
else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 ||
irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) {
*port = IFX_PCIE_PORT1;
}
#endif /* CONFIG_IFX_PCIE_2ND_CORE */
else {
printk(KERN_ERR "%s: Attempted to teardown illegal "
"MSI interrupt (%d)\n", __func__, irq);
ret = -EINVAL;
}
return ret;
}
/**
* \fn void arch_teardown_msi_irq(unsigned int irq)
* \brief Called when a device no longer needs its MSI interrupts. All
* MSI interrupts for the device are freed.
*
* \param irq The devices first irq number. There may be multple in sequence.
* \return none
* \ingroup IFX_PCIE_MSI
*/
void
arch_teardown_msi_irq(unsigned int irq)
{
int pos;
int number_irqs;
u16 bitmask;
int pcie_port;
IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__);
BUG_ON(irq > (INT_NUM_IM4_IRL0 + 31));
if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) {
return;
}
/* Shift the mask to the correct bit location, not always correct
* Probally, the first match will be chosen.
*/
for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) {
if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq)
&& (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) {
break;
}
}
if (pos >= IFX_MSI_IRQ_NUM) {
printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__);
return;
}
spin_lock(&ifx_pcie_msi_lock);
/* Disable this entry */
msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE;
msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA);
spin_unlock(&ifx_pcie_msi_lock);
/*
* Count the number of IRQs we need to free by looking at the
* msi_multiple_irq_bitmask. Each bit set means that the next
* IRQ is also owned by this device.
*/
number_irqs = 0;
while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) &&
(msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) {
number_irqs++;
}
number_irqs++;
/* Mask with one bit for each IRQ */
bitmask = (1 << number_irqs) - 1;
bitmask <<= pos;
if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) {
printk(KERN_ERR "%s: Attempted to teardown MSI "
"interrupt (%d) not in use\n", __func__, irq);
return;
}
/* Checks are done, update the in use bitmask */
spin_lock(&ifx_pcie_msi_lock);
msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask;
msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1);
spin_unlock(&ifx_pcie_msi_lock);
IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
}
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Chuanhua.Lei@infineon.com");
MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module");
MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver");

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/******************************************************************************
**
** FILE NAME : ifxmips_pcie_phy.c
** PROJECT : IFX UEIP for VRX200
** MODULES : PCIe PHY sub module
**
** DATE : 14 May 2009
** AUTHOR : Lei Chuanhua
** DESCRIPTION : PCIe Root Complex Driver
** COPYRIGHT : Copyright (c) 2009
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
** HISTORY
** $Version $Date $Author $Comment
** 0.0.1 14 May,2009 Lei Chuanhua Initial version
*******************************************************************************/
/*!
\file ifxmips_pcie_phy.c
\ingroup IFX_PCIE
\brief PCIe PHY PLL register programming source file
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/paccess.h>
#include <linux/delay.h>
#include "pcie-lantiq.h"
/* PCIe PDI only supports 16 bit operation */
#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \
((*(volatile u16 *) (__addr)) = (__data))
#define IFX_PCIE_PHY_REG_READ16(__addr) \
(*(volatile u16 *) (__addr))
#define IFX_PCIE_PHY_REG16(__addr) \
(*(volatile u16 *) (__addr))
#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \
u16 read_data; \
u16 write_data; \
read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \
write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\
IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \
} while (0)
#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */
static void
pcie_phy_comm_setup(int pcie_port)
{
/* PLL Setting */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);
/* increase the bias reference voltage */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);
/* Endcnt */
IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);
/* force */
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);
/* predrv_ser_en */
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);
/* ctrl_lim */
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);
/* ctrl */
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);
/* predrv_ser_en */
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);
/* RTERM*/
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);
/* Improved 100MHz clock output */
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);
/* Reduced CDR BW to avoid glitches */
IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);
}
#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE
static void
pcie_phy_36mhz_mode_setup(int pcie_port)
{
IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
/* en_ext_mmd_div_ratio */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
/* ext_mmd_div_ratio*/
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
/* pll_ensdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
/* en_const_sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
/* mmd */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
/* lf_mode */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
/* const_sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
/* const sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
/* pllmod */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);
IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
}
#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */
#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE
static void
pcie_phy_36mhz_ssc_mode_setup(int pcie_port)
{
IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
/* PLL Setting */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);
/* Increase the bias reference voltage */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);
/* Endcnt */
IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);
/* Force */
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);
/* Predrv_ser_en */
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);
/* ctrl_lim */
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);
/* ctrl */
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);
/* predrv_ser_en */
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);
/* RTERM*/
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);
/* en_ext_mmd_div_ratio */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
/* ext_mmd_div_ratio*/
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
/* pll_ensdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400);
/* en_const_sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
/* mmd */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
/* lf_mode */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
/* const_sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100);
/* const sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
/* pllmod */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF);
/* improved 100MHz clock output */
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);
/* reduced CDR BW to avoid glitches */
IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);
IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
}
#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */
#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE
static void
pcie_phy_25mhz_mode_setup(int pcie_port)
{
IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
/* en_const_sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
/* pll_ensdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200);
/* en_ext_mmd_div_ratio*/
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002);
/* ext_mmd_div_ratio*/
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070);
/* mmd */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000);
/* lf_mode */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000);
IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
}
#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */
#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE
static void
pcie_phy_100mhz_mode_setup(int pcie_port)
{
IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
/* en_ext_mmd_div_ratio */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
/* ext_mmd_div_ratio*/
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
/* pll_ensdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
/* en_const_sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
/* mmd */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
/* lf_mode */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
/* const_sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
/* const sdm */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
/* pllmod */
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);
IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
}
#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */
static int
pcie_phy_wait_startup_ready(int pcie_port)
{
int i;
for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) {
if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) {
break;
}
udelay(10);
}
if (i >= IFX_PCIE_PLL_TIMEOUT) {
printk(KERN_ERR "%s PLL Link timeout\n", __func__);
return -1;
}
return 0;
}
static void
pcie_phy_load_enable(int pcie_port, int slice)
{
/* Set the load_en of tx/rx slice to '1' */
switch (slice) {
case 1:
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010);
break;
case 2:
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010);
break;
case 3:
IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002);
break;
}
}
static void
pcie_phy_load_disable(int pcie_port, int slice)
{
/* set the load_en of tx/rx slice to '0' */
switch (slice) {
case 1:
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010);
break;
case 2:
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010);
break;
case 3:
IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002);
break;
}
}
static void pcie_phy_load_war(int pcie_port)
{
int slice;
for (slice = 1; slice < 4; slice++) {
pcie_phy_load_enable(pcie_port, slice);
udelay(1);
pcie_phy_load_disable(pcie_port, slice);
}
}
static void pcie_phy_tx2_modulation(int pcie_port)
{
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF);
mdelay(1);
IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF);
}
static void pcie_phy_tx1_modulation(int pcie_port)
{
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF);
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF);
mdelay(1);
IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF);
}
static void pcie_phy_tx_modulation_war(int pcie_port)
{
int i;
#define PCIE_PHY_MODULATION_NUM 5
for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) {
pcie_phy_tx2_modulation(pcie_port);
pcie_phy_tx1_modulation(pcie_port);
}
#undef PCIE_PHY_MODULATION_NUM
}
void pcie_phy_clock_mode_setup(int pcie_port)
{
pcie_pdi_big_endian(pcie_port);
/* Enable PDI to access PCIe PHY register */
pcie_pdi_pmu_enable(pcie_port);
/* Configure PLL and PHY clock */
pcie_phy_comm_setup(pcie_port);
#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE
pcie_phy_36mhz_mode_setup(pcie_port);
#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE)
pcie_phy_36mhz_ssc_mode_setup(pcie_port);
#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE)
pcie_phy_25mhz_mode_setup(pcie_port);
#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE)
pcie_phy_100mhz_mode_setup(pcie_port);
#else
#error "PCIE PHY Clock Mode must be chosen first!!!!"
#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */
/* Enable PCIe PHY and make PLL setting take effect */
pcie_phy_pmu_enable(pcie_port);
/* Check if we are in startup_ready status */
pcie_phy_wait_startup_ready(pcie_port);
pcie_phy_load_war(pcie_port);
/* Apply TX modulation workarounds */
pcie_phy_tx_modulation_war(pcie_port);
#ifdef IFX_PCI_PHY_REG_DUMP
IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n");
pcie_phy_reg_dump(pcie_port);
#endif
}

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target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.c Normal file
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target/linux/lantiq/files/drivers/net/ethernet/lantiq_vrx200.c Normal file
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/************************************************************************
*
* Copyright (c) 2005
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <linux/in.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/mm.h>
#include <linux/platform_device.h>
#include <linux/ethtool.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <asm/checksum.h>
#if 1 /** TODO: MOVE TO APPROPRIATE PLACE */
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
#define REV_MII_MODE 2
#endif
#define DRV_NAME "ifxmips_mii0"
#include <lantiq_soc.h>
#include <svip_dma.h>
#ifdef CONFIG_DEBUG_MINI_BOOT
#define IKOS_MINI_BOOT
#endif
/* debugging */
#undef INCAIP2_SW_DUMP
#define INCAIP2_SW_EMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args)
#define INCAIP2_SW_CHIP_NO 1
#define INCAIP2_SW_CHIP_ID 0
#define INCAIP2_SW_DEVICE_NO 1
#ifdef INCAIP2_SW_DEBUG_MSG
#define INCAIP2_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args)
#else
#define INCAIP2_SW_DMSG(fmt,args...)
#endif
/************************** Module Parameters *****************************/
static char *mode = "bridge";
module_param(mode, charp, 0000);
MODULE_PARM_DESC(mode, "<description>");
#ifdef HAVE_TX_TIMEOUT
static int timeout = 10*HZ;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Transmission watchdog timeout in seconds>");
#endif
#ifdef IKOS_MINI_BOOT
#ifdef CONFIG_INCAIP2
extern s32 incaip2_sw_to_mbx(struct sk_buff* skb);
#endif
extern s32 svip_sw_to_mbx(struct sk_buff* skb);
#endif
struct svip_mii_priv {
struct net_device_stats stats;
struct dma_device_info *dma_device;
struct sk_buff *skb;
};
static struct net_device *svip_mii0_dev;
static unsigned char mac_addr[MAX_ADDR_LEN];
static unsigned char my_ethaddr[MAX_ADDR_LEN];
/**
* Initialize MAC address.
* This function copies the ethernet address from kernel command line.
*
* \param line Pointer to parameter
* \return 0 OK
* \ingroup Internal
*/
static int __init svip_eth_ethaddr_setup(char *line)
{
char *ep;
int i;
memset(my_ethaddr, 0, MAX_ADDR_LEN);
/* there should really be routines to do this stuff */
for (i = 0; i < 6; i++)
{
my_ethaddr[i] = line ? simple_strtoul(line, &ep, 16) : 0;
if (line)
line = (*ep) ? ep+1 : ep;
}
INCAIP2_SW_DMSG("mac address %2x-%2x-%2x-%2x-%2x-%2x \n"
,my_ethaddr[0]
,my_ethaddr[1]
,my_ethaddr[2]
,my_ethaddr[3]
,my_ethaddr[4]
,my_ethaddr[5]);
return 0;
}
__setup("ethaddr=", svip_eth_ethaddr_setup);
/**
* Open RX DMA channels.
* This function opens all DMA rx channels.
*
* \param dma_dev pointer to DMA device information
* \ingroup Internal
*/
static void svip_eth_open_rx_dma(struct dma_device_info *dma_dev)
{
int i;
for(i=0; i<dma_dev->num_rx_chan; i++)
{
dma_dev->rx_chan[i]->open(dma_dev->rx_chan[i]);
}
}
/**
* Open TX DMA channels.
* This function opens all DMA tx channels.
*
* \param dev pointer to net device structure that comprises
* DMA device information pointed to by it's priv field.
* \ingroup Internal
*/
static void svip_eth_open_tx_dma(struct dma_device_info *dma_dev)
{
int i;
for (i=0; i<dma_dev->num_tx_chan; i++)
{
dma_dev->tx_chan[i]->open(dma_dev->tx_chan[i]);
}
}
#ifdef CONFIG_NET_HW_FLOWCONTROL
/**
* Enable receiving DMA.
* This function enables the receiving DMA channel.
*
* \param dev pointer to net device structure that comprises
* DMA device information pointed to by it's priv field.
* \ingroup Internal
*/
void svip_eth_xon(struct net_device *dev)
{
struct switch_priv *sw_dev = (struct switch_priv *)dev->priv;
struct dma_device_info* dma_dev =
(struct dma_device_info *)sw_dev->dma_device;
unsigned long flag;
local_irq_save(flag);
INCAIP2_SW_DMSG("wakeup\n");
svip_eth_open_rx_dma(dma_dev);
local_irq_restore(flag);
}
#endif /* CONFIG_NET_HW_FLOWCONTROL */
/**
* Open network device.
* This functions opens the network device and starts the interface queue.
*
* \param dev Device structure for Ethernet device
* \return 0 OK, device opened
* \return -1 Error, registering DMA device
* \ingroup API
*/
int svip_mii_open(struct net_device *dev)
{
struct svip_mii_priv *priv = netdev_priv(dev);
struct dma_device_info *dma_dev = priv->dma_device;
svip_eth_open_rx_dma(dma_dev);
svip_eth_open_tx_dma(dma_dev);
netif_start_queue(dev);
return 0;
}
/**
* Close network device.
* This functions closes the network device, which will also stop the interface
* queue.
*
* \param dev Device structure for Ethernet device
* \return 0 OK, device closed (cannot fail)
* \ingroup API
*/
int svip_mii_release(struct net_device *dev)
{
struct svip_mii_priv *priv = netdev_priv(dev);
struct dma_device_info *dma_dev = priv->dma_device;
int i;
for (i = 0; i < dma_dev->max_rx_chan_num; i++)
dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
netif_stop_queue(dev);
return 0;
}
/**
* Read data from DMA device.
* This function reads data from the DMA device. The function is called by
* the switch/DMA pseudo interrupt handler dma_intr_handler on occurence of
* a DMA receive interrupt.
*
* \param dev Pointer to network device structure
* \param dma_dev Pointer to dma device structure
* \return OK In case of successful data reception from dma
* -EIO Incorrect opt pointer provided by device
* \ingroup Internal
*/
int svip_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev)
{
struct svip_mii_priv *priv = netdev_priv(dev);
unsigned char *buf = NULL;
struct sk_buff *skb = NULL;
int len = 0;
len = dma_device_read(dma_dev, &buf, (void **)&skb);
if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) {
printk(KERN_INFO DRV_NAME ": packet too large %d\n", len);
goto mii_hw_receive_err_exit;
}
if (skb == NULL) {
printk(KERN_INFO DRV_NAME ": cannot restore pointer\n");
goto mii_hw_receive_err_exit;
}
if (len > (skb->end - skb->tail)) {
printk(KERN_INFO DRV_NAME ": BUG, len:%d end:%p tail:%p\n",
len, skb->end, skb->tail);
goto mii_hw_receive_err_exit;
}
skb_put(skb, len);
skb->dev = dev;
skb->protocol = eth_type_trans(skb, dev);
netif_rx(skb);
priv->stats.rx_packets++;
priv->stats.rx_bytes += len;
return 0;
mii_hw_receive_err_exit:
if (len == 0) {
if (skb)
dev_kfree_skb_any(skb);
priv->stats.rx_errors++;
priv->stats.rx_dropped++;
return -EIO;
} else {
return len;
}
}
/**
* Write data to Ethernet switch.
* This function writes the data comprised in skb structure via DMA to the
* Ethernet Switch. It is installed as the switch driver's hard_start_xmit
* method.
*
* \param skb Pointer to socket buffer structure that contains the data
* to be sent
* \param dev Pointer to network device structure which is used for
* data transmission
* \return 1 Transmission error
* \return 0 OK, successful data transmission
* \ingroup API
*/
static int svip_mii_hw_tx(char *buf, int len, struct net_device *dev)
{
int ret = 0;
struct svip_mii_priv *priv = netdev_priv(dev);
struct dma_device_info *dma_dev = priv->dma_device;
ret = dma_device_write(dma_dev, buf, len, priv->skb);
return ret;
}
static int svip_mii_tx(struct sk_buff *skb, struct net_device *dev)
{
int len;
char *data;
struct svip_mii_priv *priv = netdev_priv(dev);
struct dma_device_info *dma_dev = priv->dma_device;
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
data = skb->data;
priv->skb = skb;
dev->trans_start = jiffies;
/* TODO: we got more than 1 dma channel,
so we should do something intelligent here to select one */
dma_dev->current_tx_chan = 0;
wmb();
if (svip_mii_hw_tx(data, len, dev) != len) {
dev_kfree_skb_any(skb);
priv->stats.tx_errors++;
priv->stats.tx_dropped++;
} else {
priv->stats.tx_packets++;
priv->stats.tx_bytes += len;
}
return 0;
}
/**
* Transmission timeout callback.
* This functions is called when a trasmission timeout occurs. It will wake up
* the interface queue again.
*
* \param dev Device structure for Ethernet device
* \ingroup API
*/
void svip_mii_tx_timeout(struct net_device *dev)
{
int i;
struct svip_mii_priv *priv = netdev_priv(dev);
priv->stats.tx_errors++;
for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
netif_wake_queue(dev);
return;
}
/**
* Get device statistics.
* This functions returns the device statistics, stored in the device structure.
*
* \param dev Device structure for Ethernet device
* \return stats Pointer to statistics structure
* \ingroup API
*/
static struct net_device_stats *svip_get_stats(struct net_device *dev)
{
struct svip_mii_priv *priv = netdev_priv(dev);
return &priv->stats;
}
/**
* Pseudo Interrupt handler for DMA.
* This function processes DMA interrupts notified to the switch device driver.
* The function is installed at the DMA core as interrupt handler for the
* switch dma device.
* It handles the following DMA interrupts:
* passes received data to the upper layer in case of rx interrupt,
* In case of a dma receive interrupt the received data is passed to the upper layer.
* In case of a transmit buffer full interrupt the transmit queue is stopped.
* In case of a transmission complete interrupt the transmit queue is restarted.
*
* \param dma_dev pointer to dma device structure
* \param status type of interrupt being notified (RCV_INT: dma receive
* interrupt, TX_BUF_FULL_INT: transmit buffer full interrupt,
* TRANSMIT_CPT_INT: transmission complete interrupt)
* \return OK In case of successful data reception from dma
* \ingroup Internal
*/
int dma_intr_handler(struct dma_device_info *dma_dev, int status)
{
int i;
switch (status) {
case RCV_INT:
svip_mii_hw_receive(svip_mii0_dev, dma_dev);
break;
case TX_BUF_FULL_INT:
printk(KERN_INFO DRV_NAME ": tx buffer full\n");
netif_stop_queue(svip_mii0_dev);
for (i = 0; i < dma_dev->max_tx_chan_num; i++) {
if ((dma_dev->tx_chan[i])->control == LTQ_DMA_CH_ON)
dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
}
break;
case TRANSMIT_CPT_INT:
#if 0
for (i = 0; i < dma_dev->max_tx_chan_num; i++)
#if 0
dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
#else
dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i], (char *)__FUNCTION__);
#endif
netif_wake_queue(svip_mii0_dev);
#endif
break;
}
return 0;
}
/**
* Allocates buffer sufficient for Ethernet Frame.
* This function is installed as DMA callback function to be called on DMA
* receive interrupt.
*
* \param len Unused
* \param *byte_offset Pointer to byte offset
* \param **opt pointer to skb structure
* \return NULL In case of buffer allocation fails
* buffer Pointer to allocated memory
* \ingroup Internal
*/
unsigned char *svip_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt)
{
unsigned char *buffer = NULL;
struct sk_buff *skb = NULL;
skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
if (skb == NULL)
return NULL;
buffer = (unsigned char *)(skb->data);
skb_reserve(skb, 2);
*(int *)opt = (int)skb;
*byte_offset = 2;
return buffer;
}
/**
* Free DMA buffer.
* This function frees a buffer, which can be either a data buffer or an
* skb structure.
*
* \param *dataptr Pointer to data buffer
* \param *opt Pointer to skb structure
* \return 0 OK
* \ingroup Internal
*/
void svip_etop_dma_buffer_free(unsigned char *dataptr, void *opt)
{
struct sk_buff *skb = NULL;
if (opt == NULL) {
kfree(dataptr);
} else {
skb = (struct sk_buff *)opt;
dev_kfree_skb_any(skb);
}
}
static int svip_mii_dev_init(struct net_device *dev);
static const struct net_device_ops svip_eth_netdev_ops = {
.ndo_init = svip_mii_dev_init,
.ndo_open = svip_mii_open,
.ndo_stop = svip_mii_release,
.ndo_start_xmit = svip_mii_tx,
.ndo_get_stats = svip_get_stats,
.ndo_tx_timeout = svip_mii_tx_timeout,
};
//#include <linux/device.h>
/**
* Initialize switch driver.
* This functions initializes the switch driver structures and registers the
* Ethernet device.
*
* \param dev Device structure for Ethernet device
* \return 0 OK
* \return ENOMEM No memory for structures available
* \return -1 Error during DMA init or Ethernet address configuration.
* \ingroup API
*/
static int svip_mii_dev_init(struct net_device *dev)
{
int i;
struct svip_mii_priv *priv = netdev_priv(dev);
ether_setup(dev);
printk(KERN_INFO DRV_NAME ": %s is up\n", dev->name);
dev->watchdog_timeo = 10 * HZ;
memset(priv, 0, sizeof(*priv));
priv->dma_device = dma_device_reserve("SW");
if (!priv->dma_device) {
BUG();
return -ENODEV;
}
priv->dma_device->buffer_alloc = svip_etop_dma_buffer_alloc;
priv->dma_device->buffer_free = svip_etop_dma_buffer_free;
priv->dma_device->intr_handler = dma_intr_handler;
for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
priv->dma_device->rx_chan[i]->packet_size =
ETHERNET_PACKET_DMA_BUFFER_SIZE;
for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) {
priv->dma_device->tx_chan[i]->tx_weight=DEFAULT_SW_CHANNEL_WEIGHT;
priv->dma_device->tx_chan[i]->packet_size =
ETHERNET_PACKET_DMA_BUFFER_SIZE;
}
dma_device_register(priv->dma_device);
printk(KERN_INFO DRV_NAME ": using mac=");
for (i = 0; i < 6; i++) {
dev->dev_addr[i] = mac_addr[i];
printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':'));
}
return 0;
}
static void svip_mii_chip_init(int mode)
{
}
static int svip_mii_probe(struct platform_device *dev)
{
int result = 0;
unsigned char *mac = (unsigned char *)dev->dev.platform_data;
svip_mii0_dev = alloc_etherdev(sizeof(struct svip_mii_priv));
svip_mii0_dev->netdev_ops = &svip_eth_netdev_ops;
memcpy(mac_addr, mac, 6);
strcpy(svip_mii0_dev->name, "eth%d");
svip_mii_chip_init(REV_MII_MODE);
result = register_netdev(svip_mii0_dev);
if (result) {
printk(KERN_INFO DRV_NAME
": error %i registering device \"%s\"\n",
result, svip_mii0_dev->name);
goto out;
}
printk(KERN_INFO DRV_NAME ": driver loaded!\n");
out:
return result;
}
static int svip_mii_remove(struct platform_device *dev)
{
struct svip_mii_priv *priv = netdev_priv(svip_mii0_dev);
printk(KERN_INFO DRV_NAME ": cleanup\n");
dma_device_unregister(priv->dma_device);
dma_device_release(priv->dma_device);
kfree(priv->dma_device);
unregister_netdev(svip_mii0_dev);
free_netdev(svip_mii0_dev);
return 0;
}
static struct platform_driver svip_mii_driver = {
.probe = svip_mii_probe,
.remove = svip_mii_remove,
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
},
};
/**
* Initialize switch driver as module.
* This functions initializes the switch driver structures and registers the
* Ethernet device for module usage.
*
* \return 0 OK
* \return ENODEV An error occured during initialization
* \ingroup API
*/
int __init svip_mii_init(void)
{
int ret = platform_driver_register(&svip_mii_driver);
if (ret)
printk(KERN_INFO DRV_NAME
": Error registering platfom driver!\n");
return ret;
}
/**
* Remove driver module.
* This functions removes the driver and unregisters all devices.
*
* \ingroup API
*/
static void __exit svip_mii_cleanup(void)
{
platform_driver_unregister(&svip_mii_driver);
}
module_init(svip_mii_init);
module_exit(svip_mii_cleanup);
MODULE_LICENSE("GPL");

346
target/linux/lantiq/files/drivers/net/ethernet/svip_virtual_eth.c Normal file
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@ -0,0 +1,346 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
Am Campeon 1-12; 81726 Munich, Germany
THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE,
WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS
SOFTWARE IS FREE OF CHARGE.
THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS
ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING
WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP,
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE
OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD
PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL
PROPERTY INFRINGEMENT.
EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT
FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM
OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
****************************************************************************
Module : svip_virtual_eth.c
Description : This file contains network driver implementation for a
Virtual Ethernet interface. The Virtual Ethernet interface
is part of Infineon's VINETIC-SVIP Linux BSP.
*******************************************************************************/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#define SVIP_VETH_VER_STR "3.0"
#define SVIP_VETH_INFO_STR \
"@(#)SVIP virtual ethernet interface, version " SVIP_VETH_VER_STR
/******************************************************************************
* Local define/macro definitions
******************************************************************************/
struct svip_ve_priv
{
struct net_device_stats stats;
};
/******************************************************************************
* Global function declarations
******************************************************************************/
int svip_ve_rx(struct sk_buff *skb);
/******************************************************************************
* Local variable declarations
******************************************************************************/
static struct net_device *svip_ve_dev;
static int watchdog_timeout = 10*HZ;
static int (*svip_ve_mps_xmit)(struct sk_buff *skb) = NULL;
/******************************************************************************
* Global function declarations
******************************************************************************/
/**
* Called by MPS driver to register a transmit routine called for each outgoing
* VoFW0 message.
*
* \param mps_xmit pointer to transmit routine
*
* \return none
*
* \ingroup Internal
*/
void register_mps_xmit_routine(int (*mps_xmit)(struct sk_buff *skb))
{
svip_ve_mps_xmit = mps_xmit;
}
EXPORT_SYMBOL(register_mps_xmit_routine);
/**
* Returns a pointer to the routine used to deliver an incoming packet/message
* from the MPS mailbox to the networking layer. This routine is called by MPS
* driver during initialisation time.
*
* \param skb pointer to incoming socket buffer
*
* \return svip_ve_rx pointer to incoming messages delivering routine
*
* \ingroup Internal
*/
int (*register_mps_recv_routine(void)) (struct sk_buff *skb)
{
return svip_ve_rx;
}
/**
* Used to deliver outgoing packets to VoFW0 module through the MPS driver.
* Upon loading/initialisation the MPS driver is registering a transmitting
* routine, which is called here to deliver the packet to the VoFW0 module.
*
* \param skb pointer to skb containing outgoing data
* \param dev pointer to this networking device's data
*
* \return 0 on success
* \return non-zero on error
*
* \ingroup Internal
*/
static int svip_ve_xmit(struct sk_buff *skb, struct net_device *dev)
{
int err;
struct svip_ve_priv *priv = netdev_priv(dev);
struct net_device_stats *stats = &priv->stats;
stats->tx_packets++;
stats->tx_bytes += skb->len;
if (svip_ve_mps_xmit)
{
err = svip_ve_mps_xmit(skb);
if (err)
stats->tx_errors++;
dev->trans_start = jiffies;
return err;
}
else
printk(KERN_ERR "%s: MPS driver not registered, outgoing packet not delivered\n", dev->name);
dev_kfree_skb(skb);
return -1;
}
/**
* Called by MPS driver upon receipt of a new message from VoFW0 module in
* the data inbox. The packet is pushed up the IP module for further processing.
*
* \param skb pointer to skb containing the incoming message
*
* \return 0 on success
* \return non-zero on error
*
* \ingroup Internal
*/
int svip_ve_rx(struct sk_buff *skb)
{
int err;
struct svip_ve_priv *priv = netdev_priv(svip_ve_dev);
struct net_device_stats *stats = &priv->stats;
skb->dev = svip_ve_dev;
skb->protocol = eth_type_trans(skb, svip_ve_dev);
stats->rx_packets++;
stats->rx_bytes += skb->len;
err = netif_rx(skb);
switch (err)
{
case NET_RX_SUCCESS:
return 0;
break;
case NET_RX_DROP:
default:
stats->rx_dropped++;
break;
}
return 1;
}
EXPORT_SYMBOL(svip_ve_rx);
/**
* Returns a pointer to the device's networking statistics data
*
* \param dev pointer to this networking device's data
*
* \return stats pointer to this network device's statistics data
*
* \ingroup Internal
*/
static struct net_device_stats *svip_ve_get_stats(struct net_device *dev)
{
struct svip_ve_priv *priv = netdev_priv(dev);
return &priv->stats;
}
static void svip_ve_tx_timeout(struct net_device *dev)
{
struct svip_ve_priv *priv = netdev_priv(dev);
priv->stats.tx_errors++;
netif_wake_queue(dev);
}
/**
* Device open routine. Called e.g. upon setting of an IP address using,
* 'ifconfig veth0 YYY.YYY.YYY.YYY netmask ZZZ.ZZZ.ZZZ.ZZZ' or
* 'ifconfig veth0 up'
*
* \param dev pointer to this network device's data
*
* \return 0 on success
* \return non-zero on error
*
* \ingroup Internal
*/
int svip_ve_open(struct net_device *dev)
{
netif_start_queue(dev);
return 0;
}
/**
* Device close routine. Called e.g. upon calling
* 'ifconfig veth0 down'
*
* \param dev pointer to this network device's data
*
* \return 0 on success
* \return non-zero on error
*
* \ingroup Internal
*/
int svip_ve_release(struct net_device *dev)
{
netif_stop_queue(dev);
return 0;
}
static int svip_ve_dev_init(struct net_device *dev);
static const struct net_device_ops svip_virtual_eth_netdev_ops = {
.ndo_init = svip_ve_dev_init,
.ndo_open = svip_ve_open,
.ndo_stop = svip_ve_release,
.ndo_start_xmit = svip_ve_xmit,
.ndo_get_stats = svip_ve_get_stats,
.ndo_tx_timeout = svip_ve_tx_timeout,
};
/**
* Device initialisation routine which registers device interface routines.
* It is called upon execution of 'register_netdev' routine.
*
* \param dev pointer to this network device's data
*
* \return 0 on success
* \return non-zero on error
*
* \ingroup Internal
*/
static int svip_ve_dev_init(struct net_device *dev)
{
ether_setup(dev); /* assign some of the fields */
dev->watchdog_timeo = watchdog_timeout;
memset(netdev_priv(dev), 0, sizeof(struct svip_ve_priv));
dev->flags |= IFF_NOARP|IFF_PROMISC;
dev->flags &= ~IFF_MULTICAST;
/* dedicated MAC address to veth0, 00:03:19:00:15:80 */
dev->dev_addr[0] = 0x00;
dev->dev_addr[1] = 0x03;
dev->dev_addr[2] = 0x19;
dev->dev_addr[3] = 0x00;
dev->dev_addr[4] = 0x15;
dev->dev_addr[5] = 0x80;
return 0;
}
static int svip_ve_probe(struct platform_device *dev)
{
int result = 0;
svip_ve_dev = alloc_etherdev(sizeof(struct svip_ve_priv));
svip_ve_dev->netdev_ops = &svip_virtual_eth_netdev_ops;
strcpy(svip_ve_dev->name, "veth%d");
result = register_netdev(svip_ve_dev);
if (result)
{
printk(KERN_INFO "error %i registering device \"%s\"\n", result, svip_ve_dev->name);
goto out;
}
printk (KERN_INFO "%s, (c) 2009, Lantiq Deutschland GmbH\n", &SVIP_VETH_INFO_STR[4]);
out:
return result;
}
static int svip_ve_remove(struct platform_device *dev)
{
unregister_netdev(svip_ve_dev);
free_netdev(svip_ve_dev);
printk(KERN_INFO "%s removed\n", svip_ve_dev->name);
return 0;
}
static struct platform_driver svip_ve_driver = {
.probe = svip_ve_probe,
.remove = svip_ve_remove,
.driver = {
.name = "ifxmips_svip_ve",
.owner = THIS_MODULE,
},
};
/**
* Module/driver entry routine
*/
static int __init svip_ve_init_module(void)
{
int ret;
ret = platform_driver_register(&svip_ve_driver);
if (ret)
printk(KERN_INFO "SVIP: error(%d) registering virtual Ethernet driver!\n", ret);
return ret;
}
/**
* Module exit routine (never called for statically linked driver)
*/
static void __exit svip_ve_cleanup_module(void)
{
platform_driver_unregister(&svip_ve_driver);
}
module_init(svip_ve_init_module);
module_exit(svip_ve_cleanup_module);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("virtual ethernet driver for LANTIQ SVIP system");
EXPORT_SYMBOL(register_mps_recv_routine);

483
target/linux/lantiq/files/drivers/spi/spi-falcon.c Normal file
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@ -0,0 +1,483 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <lantiq_soc.h>
#define DRV_NAME "falcon_spi"
#define FALCON_SPI_XFER_BEGIN (1 << 0)
#define FALCON_SPI_XFER_END (1 << 1)
/* Bus Read Configuration Register0 */
#define LTQ_BUSRCON0 0x00000010
/* Bus Write Configuration Register0 */
#define LTQ_BUSWCON0 0x00000018
/* Serial Flash Configuration Register */
#define LTQ_SFCON 0x00000080
/* Serial Flash Time Register */
#define LTQ_SFTIME 0x00000084
/* Serial Flash Status Register */
#define LTQ_SFSTAT 0x00000088
/* Serial Flash Command Register */
#define LTQ_SFCMD 0x0000008C
/* Serial Flash Address Register */
#define LTQ_SFADDR 0x00000090
/* Serial Flash Data Register */
#define LTQ_SFDATA 0x00000094
/* Serial Flash I/O Control Register */
#define LTQ_SFIO 0x00000098
/* EBU Clock Control Register */
#define LTQ_EBUCC 0x000000C4
/* Dummy Phase Length */
#define SFCMD_DUMLEN_OFFSET 16
#define SFCMD_DUMLEN_MASK 0x000F0000
/* Chip Select */
#define SFCMD_CS_OFFSET 24
#define SFCMD_CS_MASK 0x07000000
/* field offset */
#define SFCMD_ALEN_OFFSET 20
#define SFCMD_ALEN_MASK 0x00700000
/* SCK Rise-edge Position */
#define SFTIME_SCKR_POS_OFFSET 8
#define SFTIME_SCKR_POS_MASK 0x00000F00
/* SCK Period */
#define SFTIME_SCK_PER_OFFSET 0
#define SFTIME_SCK_PER_MASK 0x0000000F
/* SCK Fall-edge Position */
#define SFTIME_SCKF_POS_OFFSET 12
#define SFTIME_SCKF_POS_MASK 0x0000F000
/* Device Size */
#define SFCON_DEV_SIZE_A23_0 0x03000000
#define SFCON_DEV_SIZE_MASK 0x0F000000
/* Read Data Position */
#define SFTIME_RD_POS_MASK 0x000F0000
/* Data Output */
#define SFIO_UNUSED_WD_MASK 0x0000000F
/* Command Opcode mask */
#define SFCMD_OPC_MASK 0x000000FF
/* dlen bytes of data to write */
#define SFCMD_DIR_WRITE 0x00000100
/* Data Length offset */
#define SFCMD_DLEN_OFFSET 9
/* Command Error */
#define SFSTAT_CMD_ERR 0x20000000
/* Access Command Pending */
#define SFSTAT_CMD_PEND 0x00400000
/* Frequency set to 100MHz. */
#define EBUCC_EBUDIV_SELF100 0x00000001
/* Serial Flash */
#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
/* 8-bit multiplexed */
#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
/* Serial Flash */
#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
/* Chip Select after opcode */
#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
struct falcon_spi {
u32 sfcmd; /* for caching of opcode, direction, ... */
struct spi_master *master;
};
int
falcon_spi_xfer(struct spi_device *spi,
struct spi_transfer *t,
unsigned long flags)
{
struct device *dev = &spi->dev;
struct falcon_spi *priv = spi_master_get_devdata(spi->master);
const u8 *txp = t->tx_buf;
u8 *rxp = t->rx_buf;
unsigned int bytelen = ((8 * t->len + 7) / 8);
unsigned int len, alen, dumlen;
u32 val;
enum {
state_init,
state_command_prepare,
state_write,
state_read,
state_disable_cs,
state_end
} state = state_init;
do {
switch (state) {
case state_init: /* detect phase of upper layer sequence */
{
/* initial write ? */
if (flags & FALCON_SPI_XFER_BEGIN) {
if (!txp) {
dev_err(dev,
"BEGIN without tx data!\n");
return -1;
}
/*
* Prepare the parts of the sfcmd register,
* which should not
* change during a sequence!
* Only exception are the length fields,
* especially alen and dumlen.
*/
priv->sfcmd = ((spi->chip_select
<< SFCMD_CS_OFFSET)
& SFCMD_CS_MASK);
priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
priv->sfcmd |= *txp;
txp++;
bytelen--;
if (bytelen) {
/*
* more data:
* maybe address and/or dummy
*/
state = state_command_prepare;
break;
} else {
dev_dbg(dev, "write cmd %02X\n",
priv->sfcmd & SFCMD_OPC_MASK);
}
}
/* continued write ? */
if (txp && bytelen) {
state = state_write;
break;
}
/* read data? */
if (rxp && bytelen) {
state = state_read;
break;
}
/* end of sequence? */
if (flags & FALCON_SPI_XFER_END)
state = state_disable_cs;
else
state = state_end;
break;
}
/* collect tx data for address and dummy phase */
case state_command_prepare:
{
/* txp is valid, already checked */
val = 0;
alen = 0;
dumlen = 0;
while (bytelen > 0) {
if (alen < 3) {
val = (val<<8)|(*txp++);
alen++;
} else if ((dumlen < 15) && (*txp == 0)) {
/*
* assume dummy bytes are set to 0
* from upper layer
*/
dumlen++;
txp++;
} else
break;
bytelen--;
}
priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
(dumlen << SFCMD_DUMLEN_OFFSET);
if (alen > 0)
ltq_ebu_w32(val, LTQ_SFADDR);
dev_dbg(dev, "write cmd %02X, alen=%d "
"(addr=%06X) dumlen=%d\n",
priv->sfcmd & SFCMD_OPC_MASK,
alen, val, dumlen);
if (bytelen > 0) {
/* continue with write */
state = state_write;
} else if (flags & FALCON_SPI_XFER_END) {
/* end of sequence? */
state = state_disable_cs;
} else {
/*
* go to end and expect another
* call (read or write)
*/
state = state_end;
}
break;
}
case state_write:
{
/* txp still valid */
priv->sfcmd |= SFCMD_DIR_WRITE;
len = 0;
val = 0;
do {
if (bytelen--)
val |= (*txp++) << (8 * len++);
if ((flags & FALCON_SPI_XFER_END)
&& (bytelen == 0)) {
priv->sfcmd &=
~SFCMD_KEEP_CS_KEEP_SELECTED;
}
if ((len == 4) || (bytelen == 0)) {
ltq_ebu_w32(val, LTQ_SFDATA);
ltq_ebu_w32(priv->sfcmd
| (len<<SFCMD_DLEN_OFFSET),
LTQ_SFCMD);
len = 0;
val = 0;
priv->sfcmd &= ~(SFCMD_ALEN_MASK
| SFCMD_DUMLEN_MASK);
}
} while (bytelen);
state = state_end;
break;
}
case state_read:
{
/* read data */
priv->sfcmd &= ~SFCMD_DIR_WRITE;
do {
if ((flags & FALCON_SPI_XFER_END)
&& (bytelen <= 4)) {
priv->sfcmd &=
~SFCMD_KEEP_CS_KEEP_SELECTED;
}
len = (bytelen > 4) ? 4 : bytelen;
bytelen -= len;
ltq_ebu_w32(priv->sfcmd
|(len<<SFCMD_DLEN_OFFSET), LTQ_SFCMD);
priv->sfcmd &= ~(SFCMD_ALEN_MASK
| SFCMD_DUMLEN_MASK);
do {
val = ltq_ebu_r32(LTQ_SFSTAT);
if (val & SFSTAT_CMD_ERR) {
/* reset error status */
dev_err(dev, "SFSTAT: CMD_ERR "
"(%x)\n", val);
ltq_ebu_w32(SFSTAT_CMD_ERR,
LTQ_SFSTAT);
return -1;
}
} while (val & SFSTAT_CMD_PEND);
val = ltq_ebu_r32(LTQ_SFDATA);
do {
*rxp = (val & 0xFF);
rxp++;
val >>= 8;
len--;
} while (len);
} while (bytelen);
state = state_end;
break;
}
case state_disable_cs:
{
priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
LTQ_SFCMD);
val = ltq_ebu_r32(LTQ_SFSTAT);
if (val & SFSTAT_CMD_ERR) {
/* reset error status */
dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT);
return -1;
}
state = state_end;
break;
}
case state_end:
break;
}
} while (state != state_end);
return 0;
}
static int
falcon_spi_setup(struct spi_device *spi)
{
struct device *dev = &spi->dev;
const u32 ebuclk = 100000000;
unsigned int i;
unsigned long flags;
dev_dbg(dev, "setup\n");
if (spi->master->bus_num > 0 || spi->chip_select > 0)
return -ENODEV;
spin_lock_irqsave(&ebu_lock, flags);
if (ebuclk < spi->max_speed_hz) {
/* set EBU clock to 100 MHz */
ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC);
i = 1; /* divider */
} else {
/* set EBU clock to 50 MHz */
ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC);
/* search for suitable divider */
for (i = 1; i < 7; i++) {
if (ebuclk / i <= spi->max_speed_hz)
break;
}
}
/* setup period of serial clock */
ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
| SFTIME_SCKR_POS_MASK
| SFTIME_SCK_PER_MASK,
(i << SFTIME_SCKR_POS_OFFSET)
| (i << (SFTIME_SCK_PER_OFFSET + 1)),
LTQ_SFTIME);
/*
* set some bits of unused_wd, to not trigger HOLD/WP
* signals on non QUAD flashes
*/
ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO);
ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
LTQ_BUSRCON0);
ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0);
/* set address wrap around to maximum for 24-bit addresses */
ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON);
spin_unlock_irqrestore(&ebu_lock, flags);
return 0;
}
static int
falcon_spi_transfer(struct spi_device *spi, struct spi_message *m)
{
struct falcon_spi *priv = spi_master_get_devdata(spi->master);
struct spi_transfer *t;
unsigned long spi_flags;
unsigned long flags;
int ret = 0;
priv->sfcmd = 0;
m->actual_length = 0;
spi_flags = FALCON_SPI_XFER_BEGIN;
list_for_each_entry(t, &m->transfers, transfer_list) {
if (list_is_last(&t->transfer_list, &m->transfers))
spi_flags |= FALCON_SPI_XFER_END;
spin_lock_irqsave(&ebu_lock, flags);
ret = falcon_spi_xfer(spi, t, spi_flags);
spin_unlock_irqrestore(&ebu_lock, flags);
if (ret)
break;
m->actual_length += t->len;
if (t->delay_usecs || t->cs_change)
BUG();
spi_flags = 0;
}
m->status = ret;
m->complete(m->context);
return 0;
}
static void
falcon_spi_cleanup(struct spi_device *spi)
{
struct device *dev = &spi->dev;
dev_dbg(dev, "cleanup\n");
}
static int __devinit
falcon_spi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct falcon_spi *priv;
struct spi_master *master;
int ret;
dev_dbg(dev, "probing\n");
master = spi_alloc_master(&pdev->dev, sizeof(*priv));
if (!master) {
dev_err(dev, "no memory for spi_master\n");
return -ENOMEM;
}
priv = spi_master_get_devdata(master);
priv->master = master;
master->mode_bits = SPI_MODE_3;
master->num_chipselect = 1;
master->bus_num = 0;
master->setup = falcon_spi_setup;
master->transfer = falcon_spi_transfer;
master->cleanup = falcon_spi_cleanup;
platform_set_drvdata(pdev, priv);
ret = spi_register_master(master);
if (ret)
spi_master_put(master);
return ret;
}
static int __devexit
falcon_spi_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct falcon_spi *priv = platform_get_drvdata(pdev);
dev_dbg(dev, "removed\n");
spi_unregister_master(priv->master);
return 0;
}
static struct platform_driver falcon_spi_driver = {
.probe = falcon_spi_probe,
.remove = __devexit_p(falcon_spi_remove),
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE
}
};
static int __init
falcon_spi_init(void)
{
return platform_driver_register(&falcon_spi_driver);
}
static void __exit
falcon_spi_exit(void)
{
platform_driver_unregister(&falcon_spi_driver);
}
module_init(falcon_spi_init);
module_exit(falcon_spi_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");

1070
target/linux/lantiq/files/drivers/spi/spi-xway.c Normal file
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955
target/linux/lantiq/files/drivers/spi/spi_svip.c Normal file
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@ -0,0 +1,955 @@
/************************************************************************
*
* Copyright (c) 2008
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* Inspired by Atmel AT32/AT91 SPI Controller driver
* Copyright (c) 2006 Atmel Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <asm/io.h>
#include <status_reg.h>
#include <base_reg.h>
#include <ssc_reg.h>
#include <sys0_reg.h>
#include <sys1_reg.h>
#define SFRAME_SIZE 512 /* bytes */
#define FIFO_HEADROOM 2 /* words */
#define SVIP_SSC_RFIFO_WORDS 8
enum svip_ssc_dir {
SSC_RXTX,
SSC_RX,
SSC_TX,
SSC_UNDEF
};
/*
* The core SPI transfer engine just talks to a register bank to set up
* DMA transfers; transfer queue progress is driven by IRQs. The clock
* framework provides the base clock, subdivided for each spi_device.
*/
struct svip_ssc_device {
struct svip_reg_ssc *regs;
enum svip_ssc_dir bus_dir;
struct spi_device *stay;
u8 stopping;
struct list_head queue;
struct spi_transfer *current_transfer;
int remaining_bytes;
int rx_bytes;
int tx_bytes;
char intname[4][16];
spinlock_t lock;
};
static int svip_ssc_setup(struct spi_device *spi);
extern unsigned int ltq_get_fbs0_hz(void);
static void cs_activate(struct svip_ssc_device *ssc_dev, struct spi_device *spi)
{
ssc_dev->regs->whbgpostat = 0x0001 << spi->chip_select; /* activate the chip select */
}
static void cs_deactivate(struct svip_ssc_device *ssc_dev, struct spi_device *spi)
{
ssc_dev->regs->whbgpostat = 0x0100 << spi->chip_select; /* deactivate the chip select */
}
/*
* "Normally" returns Byte Valid = 4.
* If the unaligned remainder of the packet is 3 bytes, these have to be
* transferred as a combination of a 16-bit and a 8-bit FPI transfer. For
* 2 or 1 remaining bytes a single 16-bit or 8-bit transfer will do.
*/
static int inline _estimate_bv(int byte_pos, int bytelen)
{
int remainder = bytelen % 4;
if (byte_pos < (bytelen - remainder))
return 4;
if (remainder == 3)
{
if (byte_pos == (bytelen - remainder))
return 2;
else
return 1;
}
return remainder;
}
/*
* Submit next transfer.
* lock is held, spi irq is blocked
*/
static void svip_ssc_next_xfer(struct spi_master *master,
struct spi_message *msg)
{
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
struct spi_transfer *xfer;
unsigned char *buf_ptr;
xfer = ssc_dev->current_transfer;
if (!xfer || ssc_dev->remaining_bytes == 0) {
if (xfer)
xfer = list_entry(xfer->transfer_list.next,
struct spi_transfer, transfer_list);
else
xfer = list_entry(msg->transfers.next,
struct spi_transfer, transfer_list);
ssc_dev->remaining_bytes = xfer->len;
ssc_dev->rx_bytes = 0;
ssc_dev->tx_bytes = 0;
ssc_dev->current_transfer = xfer;
ssc_dev->regs->sfcon = 0; /* reset Serial Framing */
/* enable and flush RX/TX FIFO */
ssc_dev->regs->rxfcon =
SSC_RXFCON_RXFITL_VAL(SVIP_SSC_RFIFO_WORDS-FIFO_HEADROOM) |
SSC_RXFCON_RXFLU | /* Receive FIFO Flush */
SSC_RXFCON_RXFEN; /* Receive FIFO Enable */
ssc_dev->regs->txfcon =
SSC_TXFCON_TXFITL_VAL(FIFO_HEADROOM) |
SSC_TXFCON_TXFLU | /* Transmit FIFO Flush */
SSC_TXFCON_TXFEN; /* Transmit FIFO Enable */
asm("sync");
/* select mode RXTX, RX or TX */
if (xfer->rx_buf && xfer->tx_buf) /* RX and TX */
{
if (ssc_dev->bus_dir != SSC_RXTX)
{
ssc_dev->regs->mcon &= ~(SSC_MCON_RXOFF | SSC_MCON_TXOFF);
ssc_dev->bus_dir = SSC_RXTX;
ssc_dev->regs->irnen = SSC_IRNEN_T | SSC_IRNEN_F | SSC_IRNEN_E;
}
ssc_dev->regs->sfcon =
SSC_SFCON_PLEN_VAL(0) |
SSC_SFCON_DLEN_VAL(((xfer->len-1)%SFRAME_SIZE)*8+7) |
SSC_SFCON_STOP |
SSC_SFCON_ICLK_VAL(2) |
SSC_SFCON_IDAT_VAL(2) |
SSC_SFCON_IAEN |
SSC_SFCON_SFEN;
}
else if (xfer->rx_buf) /* RX only */
{
if (ssc_dev->bus_dir != SSC_RX)
{
ssc_dev->regs->mcon =
(ssc_dev->regs->mcon | SSC_MCON_TXOFF) & ~SSC_MCON_RXOFF;
ssc_dev->bus_dir = SSC_RX;
ssc_dev->regs->irnen = SSC_IRNEN_R | SSC_IRNEN_E;
}
/* Initiate clock generation for Rx-Only Transfer. In case of RX-only transfer,
* rx_bytes represents the number of already requested bytes.
*/
ssc_dev->rx_bytes = min(xfer->len, (unsigned)(SVIP_SSC_RFIFO_WORDS*4));
ssc_dev->regs->rxreq = ssc_dev->rx_bytes;
}
else /* TX only */
{
if (ssc_dev->bus_dir != SSC_TX)
{
ssc_dev->regs->mcon =
(ssc_dev->regs->mcon | SSC_MCON_RXOFF) & ~SSC_MCON_TXOFF;
ssc_dev->bus_dir = SSC_TX;
ssc_dev->regs->irnen =
SSC_IRNEN_T | SSC_IRNEN_F | SSC_IRNEN_E;
}
ssc_dev->regs->sfcon =
SSC_SFCON_PLEN_VAL(0) |
SSC_SFCON_DLEN_VAL(((xfer->len-1)%SFRAME_SIZE)*8+7) |
SSC_SFCON_STOP |
SSC_SFCON_ICLK_VAL(2) |
SSC_SFCON_IDAT_VAL(2) |
SSC_SFCON_IAEN |
SSC_SFCON_SFEN;
}
}
if (xfer->tx_buf)
{
int outstanding;
int i;
int fstat = ssc_dev->regs->fstat;
int txffl = SSC_FSTAT_TXFFL_GET(fstat);
int rxffl = SSC_FSTAT_RXFFL_GET(fstat);
outstanding = txffl;
if (xfer->rx_buf)
{
outstanding += rxffl;
if (SSC_STATE_BSY_GET(ssc_dev->regs->state))
outstanding++;
while (rxffl) /* is 0 in TX-Only mode */
{
unsigned int rb;
int rxbv = _estimate_bv(ssc_dev->rx_bytes, xfer->len);
rb = ssc_dev->regs->rb;
for (i=0; i<rxbv; i++)
{
((unsigned char*)xfer->rx_buf)[ssc_dev->rx_bytes] =
(rb >> ((rxbv-i-1)*8)) & 0xFF;
ssc_dev->rx_bytes++;
}
rxffl--;
outstanding--;
}
ssc_dev->remaining_bytes = xfer->len - ssc_dev->rx_bytes;
}
/* for last Tx cycle set TxFifo threshold to 0 */
if ((xfer->len - ssc_dev->tx_bytes) <=
(4*(SVIP_SSC_RFIFO_WORDS-1-outstanding)))
{
ssc_dev->regs->txfcon = SSC_TXFCON_TXFITL_VAL(0) |
SSC_TXFCON_TXFEN;
}
while ((ssc_dev->tx_bytes < xfer->len) &&
(outstanding < (SVIP_SSC_RFIFO_WORDS-1)))
{
unsigned int tb = 0;
int txbv = _estimate_bv(ssc_dev->tx_bytes, xfer->len);
for (i=0; i<txbv; i++)
{
tb |= ((unsigned char*)xfer->tx_buf)[ssc_dev->tx_bytes] <<
((txbv-i-1)*8);
ssc_dev->tx_bytes++;
}
switch(txbv)
{
#ifdef __BIG_ENDIAN
case 1:
*((unsigned char *)(&(ssc_dev->regs->tb))+3) = tb & 0xFF;
break;
case 2:
*((unsigned short *)(&(ssc_dev->regs->tb))+1) = tb & 0xFFFF;
break;
#else /* __LITTLE_ENDIAN */
case 1:
*((unsigned char *)(&(ssc_dev->regs->tb))) = tb & 0xFF;
break;
case 2:
*((unsigned short *)(&(ssc_dev->regs->tb))) = tb & 0xFFFF;
break;
#endif
default:
ssc_dev->regs->tb = tb;
}
outstanding++;
}
}
else /* xfer->tx_buf == NULL -> RX only! */
{
int j;
int rxffl = SSC_FSTAT_RXFFL_GET(ssc_dev->regs->fstat);
int rxbv = 0;
unsigned int rbuf;
buf_ptr = (unsigned char*)xfer->rx_buf +
(xfer->len - ssc_dev->remaining_bytes);
for (j = 0; j < rxffl; j++)
{
rxbv = SSC_STATE_RXBV_GET(ssc_dev->regs->state);
rbuf = ssc_dev->regs->rb;
if (rxbv == 4)
{
*((unsigned int*)buf_ptr+j) = ntohl(rbuf);
}
else
{
int b;
#ifdef __BIG_ENDIAN
for (b = 0; b < rxbv; b++)
{
buf_ptr[4*j+b] = ((unsigned char*)(&rbuf))[4-rxbv+b];
}
#else /* __LITTLE_ENDIAN */
for (b = 0; b < rxbv; b++)
{
buf_ptr[4*j+b] = ((unsigned char*)(&rbuf))[rxbv-1-b];
}
#endif
}
ssc_dev->remaining_bytes -= rxbv;
}
if ((ssc_dev->rx_bytes < xfer->len) &&
!SSC_STATE_BSY_GET(ssc_dev->regs->state))
{
int rxreq = min(xfer->len - ssc_dev->rx_bytes,
(unsigned)(SVIP_SSC_RFIFO_WORDS*4));
ssc_dev->rx_bytes += rxreq;
ssc_dev->regs->rxreq = rxreq;
}
if (ssc_dev->remaining_bytes < 0)
{
printk("ssc_dev->remaining_bytes = %d! xfer->len = %d, "
"rxffl=%d, rxbv=%d\n", ssc_dev->remaining_bytes, xfer->len,
rxffl, rxbv);
ssc_dev->remaining_bytes = 0;
}
}
}
/*
* Submit next message.
* lock is held
*/
static void svip_ssc_next_message(struct spi_master *master)
{
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
struct spi_message *msg;
struct spi_device *spi;
BUG_ON(ssc_dev->current_transfer);
msg = list_entry(ssc_dev->queue.next, struct spi_message, queue);
spi = msg->spi;
dev_dbg(master->dev.parent, "start message %p on %p\n", msg, spi);
/* select chip if it's not still active */
if (ssc_dev->stay) {
if (ssc_dev->stay != spi) {
cs_deactivate(ssc_dev, ssc_dev->stay);
svip_ssc_setup(spi);
cs_activate(ssc_dev, spi);
}
ssc_dev->stay = NULL;
}
else {
svip_ssc_setup(spi);
cs_activate(ssc_dev, spi);
}
svip_ssc_next_xfer(master, msg);
}
/*
* Report message completion.
* lock is held
*/
static void
svip_ssc_msg_done(struct spi_master *master, struct svip_ssc_device *ssc_dev,
struct spi_message *msg, int status, int stay)
{
if (!stay || status < 0)
cs_deactivate(ssc_dev, msg->spi);
else
ssc_dev->stay = msg->spi;
list_del(&msg->queue);
msg->status = status;
dev_dbg(master->dev.parent,
"xfer complete: %u bytes transferred\n",
msg->actual_length);
spin_unlock(&ssc_dev->lock);
msg->complete(msg->context);
spin_lock(&ssc_dev->lock);
ssc_dev->current_transfer = NULL;
/* continue if needed */
if (list_empty(&ssc_dev->queue) || ssc_dev->stopping)
; /* TODO: disable hardware */
else
svip_ssc_next_message(master);
}
static irqreturn_t svip_ssc_eir_handler(int irq, void *dev_id)
{
struct platform_device *pdev = (struct platform_device*)dev_id;
struct spi_master *master = platform_get_drvdata(pdev);
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
dev_err (&pdev->dev, "ERROR: errirq. STATE = 0x%0lx\n",
ssc_dev->regs->state);
return IRQ_HANDLED;
}
static irqreturn_t svip_ssc_rir_handler(int irq, void *dev_id)
{
struct platform_device *pdev = (struct platform_device*)dev_id;
struct spi_master *master = platform_get_drvdata(pdev);
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
struct spi_message *msg;
struct spi_transfer *xfer;
xfer = ssc_dev->current_transfer;
msg = list_entry(ssc_dev->queue.next, struct spi_message, queue);
/* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt
* handler for spurious Interrupts!
*/
if (!xfer) {
dev_dbg(master->dev.parent,
"%s(%d): xfer = NULL\n", __FUNCTION__, irq);
goto out;
}
if ( !(xfer->rx_buf) ) {
dev_dbg(master->dev.parent,
"%s(%d): xfer->rx_buf = NULL\n", __FUNCTION__, irq);
goto out;
}
if (ssc_dev->remaining_bytes > 0)
{
/*
* Keep going, we still have data to send in
* the current transfer.
*/
svip_ssc_next_xfer(master, msg);
}
if (ssc_dev->remaining_bytes == 0)
{
msg->actual_length += xfer->len;
if (msg->transfers.prev == &xfer->transfer_list) {
/* report completed message */
svip_ssc_msg_done(master, ssc_dev, msg, 0,
xfer->cs_change);
}
else {
if (xfer->cs_change) {
cs_deactivate(ssc_dev, msg->spi);
udelay(1); /* not nice in interrupt context */
cs_activate(ssc_dev, msg->spi);
}
/* Not done yet. Submit the next transfer. */
svip_ssc_next_xfer(master, msg);
}
}
out:
return IRQ_HANDLED;
}
static irqreturn_t svip_ssc_tir_handler(int irq, void *dev_id)
{
struct platform_device *pdev = (struct platform_device*)dev_id;
struct spi_master *master = platform_get_drvdata(pdev);
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
struct spi_message *msg;
struct spi_transfer *xfer;
int tx_remain;
xfer = ssc_dev->current_transfer;
msg = list_entry(ssc_dev->queue.next, struct spi_message, queue);
/* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt
* handler for spurious Interrupts!
*/
if (!xfer) {
dev_dbg(master->dev.parent,
"%s(%d): xfer = NULL\n", __FUNCTION__, irq);
goto out;
}
if ( !(xfer->tx_buf) ) {
dev_dbg(master->dev.parent,
"%s(%d): xfer->tx_buf = NULL\n", __FUNCTION__, irq);
goto out;
}
if (ssc_dev->remaining_bytes > 0)
{
tx_remain = xfer->len - ssc_dev->tx_bytes;
if ( tx_remain == 0 )
{
dev_dbg(master->dev.parent,
"%s(%d): tx_remain = 0\n", __FUNCTION__, irq);
}
else
/*
* Keep going, we still have data to send in
* the current transfer.
*/
svip_ssc_next_xfer(master, msg);
}
out:
return IRQ_HANDLED;
}
static irqreturn_t svip_ssc_fir_handler(int irq, void *dev_id)
{
struct platform_device *pdev = (struct platform_device*)dev_id;
struct spi_master *master = platform_get_drvdata(pdev);
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
struct spi_message *msg;
struct spi_transfer *xfer;
xfer = ssc_dev->current_transfer;
msg = list_entry(ssc_dev->queue.next, struct spi_message, queue);
/* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt
* handler for spurious Interrupts!
*/
if (!xfer) {
dev_dbg(master->dev.parent,
"%s(%d): xfer = NULL\n", __FUNCTION__, irq);
goto out;
}
if ( !(xfer->tx_buf) ) {
dev_dbg(master->dev.parent,
"%s(%d): xfer->tx_buf = NULL\n", __FUNCTION__, irq);
goto out;
}
if (ssc_dev->remaining_bytes > 0)
{
int tx_remain = xfer->len - ssc_dev->tx_bytes;
if (tx_remain == 0)
{
/* Frame interrupt gets raised _before_ last Rx interrupt */
if (xfer->rx_buf)
{
svip_ssc_next_xfer(master, msg);
if (ssc_dev->remaining_bytes)
printk("expected RXTX transfer to be complete!\n");
}
ssc_dev->remaining_bytes = 0;
}
else
{
ssc_dev->regs->sfcon = SSC_SFCON_PLEN_VAL(0) |
SSC_SFCON_DLEN_VAL(SFRAME_SIZE*8-1) |
SSC_SFCON_STOP |
SSC_SFCON_ICLK_VAL(2) |
SSC_SFCON_IDAT_VAL(2) |
SSC_SFCON_IAEN |
SSC_SFCON_SFEN;
}
}
if (ssc_dev->remaining_bytes == 0)
{
msg->actual_length += xfer->len;
if (msg->transfers.prev == &xfer->transfer_list) {
/* report completed message */
svip_ssc_msg_done(master, ssc_dev, msg, 0,
xfer->cs_change);
}
else {
if (xfer->cs_change) {
cs_deactivate(ssc_dev, msg->spi);
udelay(1); /* not nice in interrupt context */
cs_activate(ssc_dev, msg->spi);
}
/* Not done yet. Submit the next transfer. */
svip_ssc_next_xfer(master, msg);
}
}
out:
return IRQ_HANDLED;
}
/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP)
static int svip_ssc_setup(struct spi_device *spi)
{
struct spi_master *master = spi->master;
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
unsigned int bits = spi->bits_per_word;
unsigned int br, sck_hz = spi->max_speed_hz;
unsigned long flags;
if (ssc_dev->stopping)
return -ESHUTDOWN;
if (spi->chip_select >= master->num_chipselect) {
dev_dbg(&spi->dev,
"setup: invalid chipselect %u (%u defined)\n",
spi->chip_select, master->num_chipselect);
return -EINVAL;
}
if (bits == 0)
bits = 8;
if (bits != 8) {
dev_dbg(&spi->dev,
"setup: invalid bits_per_word %u (expect 8)\n",
bits);
return -EINVAL;
}
if (spi->mode & ~MODEBITS) {
dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
spi->mode & ~MODEBITS);
return -EINVAL;
}
/* Disable SSC */
ssc_dev->regs->whbstate = SSC_WHBSTATE_CLREN;
if (sck_hz == 0)
sck_hz = 10000;
br = ltq_get_fbs0_hz()/(2 *sck_hz);
if (ltq_get_fbs0_hz()%(2 *sck_hz) == 0)
br = br -1;
ssc_dev->regs->br = br;
/* set Control Register */
ssc_dev->regs->mcon = SSC_MCON_ENBV |
SSC_MCON_RUEN |
SSC_MCON_TUEN |
SSC_MCON_AEN |
SSC_MCON_REN |
SSC_MCON_TEN |
(spi->mode & SPI_CPOL ? SSC_MCON_PO : 0) | /* Clock Polarity */
(spi->mode & SPI_CPHA ? 0 : SSC_MCON_PH) | /* Tx on trailing edge */
(spi->mode & SPI_LOOP ? SSC_MCON_LB : 0) | /* Loopback */
(spi->mode & SPI_LSB_FIRST ? 0 : SSC_MCON_HB); /* MSB first */
ssc_dev->bus_dir = SSC_UNDEF;
/* Enable SSC */
ssc_dev->regs->whbstate = SSC_WHBSTATE_SETEN;
asm("sync");
spin_lock_irqsave(&ssc_dev->lock, flags);
if (ssc_dev->stay == spi)
ssc_dev->stay = NULL;
cs_deactivate(ssc_dev, spi);
spin_unlock_irqrestore(&ssc_dev->lock, flags);
dev_dbg(&spi->dev,
"setup: %u Hz bpw %u mode 0x%02x cs %u\n",
sck_hz, bits, spi->mode, spi->chip_select);
return 0;
}
static int svip_ssc_transfer(struct spi_device *spi, struct spi_message *msg)
{
struct spi_master *master = spi->master;
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
struct spi_transfer *xfer;
unsigned long flags;
dev_dbg(&spi->dev, "new message %p submitted\n", msg);
if (unlikely(list_empty(&msg->transfers)
|| !spi->max_speed_hz)) {
return -EINVAL;
}
if (ssc_dev->stopping)
return -ESHUTDOWN;
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
if (!(xfer->tx_buf || xfer->rx_buf) || (xfer->len == 0)) {
dev_dbg(&spi->dev, "missing rx or tx buf\n");
return -EINVAL;
}
/* FIXME implement these protocol options!! */
if (xfer->bits_per_word || xfer->speed_hz) {
dev_dbg(&spi->dev, "no protocol options yet\n");
return -ENOPROTOOPT;
}
#ifdef VERBOSE
dev_dbg(spi->dev,
" xfer %p: len %u tx %p/%08x rx %p/%08x\n",
xfer, xfer->len,
xfer->tx_buf, xfer->tx_dma,
xfer->rx_buf, xfer->rx_dma);
#endif
}
msg->status = -EINPROGRESS;
msg->actual_length = 0;
spin_lock_irqsave(&ssc_dev->lock, flags);
list_add_tail(&msg->queue, &ssc_dev->queue);
if (!ssc_dev->current_transfer)
{
/* start transmission machine, if not started yet */
svip_ssc_next_message(master);
}
spin_unlock_irqrestore(&ssc_dev->lock, flags);
return 0;
}
static void svip_ssc_cleanup(struct spi_device *spi)
{
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(spi->master);
unsigned long flags;
if (!spi->controller_state)
return;
spin_lock_irqsave(&ssc_dev->lock, flags);
if (ssc_dev->stay == spi) {
ssc_dev->stay = NULL;
cs_deactivate(ssc_dev, spi);
}
spin_unlock_irqrestore(&ssc_dev->lock, flags);
}
/*-------------------------------------------------------------------------*/
static int __init svip_ssc_probe(struct platform_device *pdev)
{
int ret;
struct spi_master *master;
struct svip_ssc_device *ssc_dev;
struct resource *res_regs;
int irq;
ret = -ENOMEM;
/* setup spi core then atmel-specific driver state */
master = spi_alloc_master(&pdev->dev, sizeof (*ssc_dev));
if (!master)
{
dev_err (&pdev->dev, "ERROR: no memory for master spi\n");
goto errout;
}
ssc_dev = spi_master_get_devdata(master);
platform_set_drvdata(pdev, master);
master->bus_num = pdev->id;
master->num_chipselect = 8;
master->mode_bits = MODEBITS;
master->setup = svip_ssc_setup;
master->transfer = svip_ssc_transfer;
master->cleanup = svip_ssc_cleanup;
spin_lock_init(&ssc_dev->lock);
INIT_LIST_HEAD(&ssc_dev->queue);
/* retrive register configration */
res_regs = platform_get_resource_byname (pdev, IORESOURCE_MEM, "regs");
if (NULL == res_regs)
{
dev_err (&pdev->dev, "ERROR: missed 'regs' resource\n");
goto spierr;
}
ssc_dev->regs = (struct svip_reg_ssc*)KSEG1ADDR(res_regs->start);
irq = platform_get_irq_byname (pdev, "tx");
if (irq < 0)
goto irqerr;
sprintf(ssc_dev->intname[0], "%s_tx", pdev->name);
ret = devm_request_irq(&pdev->dev, irq, svip_ssc_tir_handler,
IRQF_DISABLED, ssc_dev->intname[0], pdev);
if (ret != 0)
goto irqerr;
irq = platform_get_irq_byname (pdev, "rx");
if (irq < 0)
goto irqerr;
sprintf(ssc_dev->intname[1], "%s_rx", pdev->name);
ret = devm_request_irq(&pdev->dev, irq, svip_ssc_rir_handler,
IRQF_DISABLED, ssc_dev->intname[1], pdev);
if (ret != 0)
goto irqerr;
irq = platform_get_irq_byname (pdev, "err");
if (irq < 0)
goto irqerr;
sprintf(ssc_dev->intname[2], "%s_err", pdev->name);
ret = devm_request_irq(&pdev->dev, irq, svip_ssc_eir_handler,
IRQF_DISABLED, ssc_dev->intname[2], pdev);
if (ret != 0)
goto irqerr;
irq = platform_get_irq_byname (pdev, "frm");
if (irq < 0)
goto irqerr;
sprintf(ssc_dev->intname[3], "%s_frm", pdev->name);
ret = devm_request_irq(&pdev->dev, irq, svip_ssc_fir_handler,
IRQF_DISABLED, ssc_dev->intname[3], pdev);
if (ret != 0)
goto irqerr;
/*
* Initialize the Hardware
*/
/* Clear enable bit, i.e. put SSC into configuration mode */
ssc_dev->regs->whbstate = SSC_WHBSTATE_CLREN;
/* enable SSC core to run at fpi clock */
ssc_dev->regs->clc = SSC_CLC_RMC_VAL(1);
asm("sync");
/* GPIO CS */
ssc_dev->regs->gpocon = SSC_GPOCON_ISCSBN_VAL(0xFF);
ssc_dev->regs->whbgpostat = SSC_WHBGPOSTAT_SETOUTN_VAL(0xFF); /* CS to high */
/* Set Master mode */
ssc_dev->regs->whbstate = SSC_WHBSTATE_SETMS;
/* enable and flush RX/TX FIFO */
ssc_dev->regs->rxfcon = SSC_RXFCON_RXFITL_VAL(SVIP_SSC_RFIFO_WORDS-FIFO_HEADROOM) |
SSC_RXFCON_RXFLU | /* Receive FIFO Flush */
SSC_RXFCON_RXFEN; /* Receive FIFO Enable */
ssc_dev->regs->txfcon = SSC_TXFCON_TXFITL_VAL(FIFO_HEADROOM) |
SSC_TXFCON_TXFLU | /* Transmit FIFO Flush */
SSC_TXFCON_TXFEN; /* Transmit FIFO Enable */
asm("sync");
/* enable IRQ */
ssc_dev->regs->irnen = SSC_IRNEN_E;
dev_info(&pdev->dev, "controller at 0x%08lx (irq %d)\n",
(unsigned long)ssc_dev->regs, platform_get_irq_byname (pdev, "rx"));
ret = spi_register_master(master);
if (ret)
goto out_reset_hw;
return 0;
out_reset_hw:
irqerr:
devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "tx"), pdev);
devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "rx"), pdev);
devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "err"), pdev);
devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "frm"), pdev);
spierr:
spi_master_put(master);
errout:
return ret;
}
static int __exit svip_ssc_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
struct spi_message *msg;
/* reset the hardware and block queue progress */
spin_lock_irq(&ssc_dev->lock);
ssc_dev->stopping = 1;
/* TODO: shutdown hardware */
spin_unlock_irq(&ssc_dev->lock);
/* Terminate remaining queued transfers */
list_for_each_entry(msg, &ssc_dev->queue, queue) {
/* REVISIT unmapping the dma is a NOP on ARM and AVR32
* but we shouldn't depend on that...
*/
msg->status = -ESHUTDOWN;
msg->complete(msg->context);
}
devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "tx"), pdev);
devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "rx"), pdev);
devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "err"), pdev);
devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "frm"), pdev);
spi_unregister_master(master);
platform_set_drvdata(pdev, NULL);
spi_master_put(master);
return 0;
}
#ifdef CONFIG_PM
static int svip_ssc_suspend(struct platform_device *pdev, pm_message_t mesg)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
clk_disable(ssc_dev->clk);
return 0;
}
static int svip_ssc_resume(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master);
clk_enable(ssc_dev->clk);
return 0;
}
#endif
static struct platform_driver svip_ssc_driver = {
.driver = {
.name = "ifx_ssc",
.owner = THIS_MODULE,
},
.probe = svip_ssc_probe,
#ifdef CONFIG_PM
.suspend = svip_ssc_suspend,
.resume = svip_ssc_resume,
#endif
.remove = __exit_p(svip_ssc_remove)
};
int __init svip_ssc_init(void)
{
return platform_driver_register(&svip_ssc_driver);
}
void __exit svip_ssc_exit(void)
{
platform_driver_unregister(&svip_ssc_driver);
}
module_init(svip_ssc_init);
module_exit(svip_ssc_exit);
MODULE_ALIAS("platform:ifx_ssc");
MODULE_DESCRIPTION("Lantiq SSC Controller driver");
MODULE_AUTHOR("Andreas Schmidt <andreas.schmidt@infineon.com>");
MODULE_AUTHOR("Jevgenijs Grigorjevs <Jevgenijs.Grigorjevs@lantiq.com>");
MODULE_LICENSE("GPL");

37
target/linux/lantiq/files/drivers/usb/dwc_otg/Kconfig Normal file
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@ -0,0 +1,37 @@
config DWC_OTG
tristate "Synopsis DWC_OTG support"
depends on USB
help
This driver supports Synopsis DWC_OTG IP core
embebbed on many SOCs (ralink, infineon, etc)
choice
prompt "USB Operation Mode"
depends on DWC_OTG
default DWC_OTG_HOST_ONLY
config DWC_OTG_HOST_ONLY
bool "HOST ONLY MODE"
depends on DWC_OTG
#config DWC_OTG_DEVICE_ONLY
# bool "DEVICE ONLY MODE"
# depends on DWC_OTG
endchoice
choice
prompt "Platform"
depends on DWC_OTG
default DWC_OTG_LANTIQ
config DWC_OTG_LANTIQ
bool "Lantiq"
depends on LANTIQ
help
Danube USB Host Controller
platform support
endchoice
config DWC_OTG_DEBUG
bool "Enable debug mode"
depends on DWC_OTG

39
target/linux/lantiq/files/drivers/usb/dwc_otg/Makefile Normal file
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@ -0,0 +1,39 @@
#
# Makefile for DWC_otg Highspeed USB controller driver
#
ifeq ($(CONFIG_DWC_OTG_DEBUG),y)
EXTRA_CFLAGS += -DDEBUG
endif
# Use one of the following flags to compile the software in host-only or
# device-only mode based on the configuration selected by the user
ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
EXTRA_CFLAGS += -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY
EXTRA_CFLAGS += -DDWC_OTG_EN_ISOC -DDWC_EN_ISOC
else ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y)
EXTRA_CFLAGS += -DDWC_OTG_DEVICE_ONLY
else
EXTRA_CFLAGS += -DDWC_OTG_MODE
endif
# EXTRA_CFLAGS += -DDWC_HS_ELECT_TST
# EXTRA_CFLAGS += -DDWC_OTG_EXT_CHG_PUMP
ifeq ($(CONFIG_DWC_OTG_LANTIQ),y)
EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -D__KERNEL__
endif
ifeq ($(CONFIG_DWC_OTG_LANTIQ),m)
EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_HOST_ONLY -DMODULE -D__KERNEL__ -DDEBUG
endif
obj-$(CONFIG_DWC_OTG) := dwc_otg.o
dwc_otg-objs := dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
#dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
dwc_otg-objs += dwc_otg_attr.o
dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
dwc_otg-objs += dwc_otg_ifx.o
dwc_otg-objs += dwc_otg_driver.o
#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o
#dwc_otg_ifx-objs := dwc_otg_ifx.o

802
target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.c Normal file
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@ -0,0 +1,802 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
/** @file
*
* The diagnostic interface will provide access to the controller for
* bringing up the hardware and testing. The Linux driver attributes
* feature will be used to provide the Linux Diagnostic
* Interface. These attributes are accessed through sysfs.
*/
/** @page "Linux Module Attributes"
*
* The Linux module attributes feature is used to provide the Linux
* Diagnostic Interface. These attributes are accessed through sysfs.
* The diagnostic interface will provide access to the controller for
* bringing up the hardware and testing.
The following table shows the attributes.
<table>
<tr>
<td><b> Name</b></td>
<td><b> Description</b></td>
<td><b> Access</b></td>
</tr>
<tr>
<td> mode </td>
<td> Returns the current mode: 0 for device mode, 1 for host mode</td>
<td> Read</td>
</tr>
<tr>
<td> hnpcapable </td>
<td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
Read returns the current value.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> srpcapable </td>
<td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
Read returns the current value.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> hnp </td>
<td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> srp </td>
<td> Initiates the Session Request Protocol. Read returns the status.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> buspower </td>
<td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
<td> Read/Write</td>
</tr>
<tr>
<td> bussuspend </td>
<td> Suspends the USB bus.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> busconnected </td>
<td> Gets the connection status of the bus</td>
<td> Read</td>
</tr>
<tr>
<td> gotgctl </td>
<td> Gets or sets the Core Control Status Register.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gusbcfg </td>
<td> Gets or sets the Core USB Configuration Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> grxfsiz </td>
<td> Gets or sets the Receive FIFO Size Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gnptxfsiz </td>
<td> Gets or sets the non-periodic Transmit Size Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gpvndctl </td>
<td> Gets or sets the PHY Vendor Control Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> ggpio </td>
<td> Gets the value in the lower 16-bits of the General Purpose IO Register
or sets the upper 16 bits.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> guid </td>
<td> Gets or sets the value of the User ID Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gsnpsid </td>
<td> Gets the value of the Synopsys ID Regester</td>
<td> Read</td>
</tr>
<tr>
<td> devspeed </td>
<td> Gets or sets the device speed setting in the DCFG register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> enumspeed </td>
<td> Gets the device enumeration Speed.</td>
<td> Read</td>
</tr>
<tr>
<td> hptxfsiz </td>
<td> Gets the value of the Host Periodic Transmit FIFO</td>
<td> Read</td>
</tr>
<tr>
<td> hprt0 </td>
<td> Gets or sets the value in the Host Port Control and Status Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regoffset </td>
<td> Sets the register offset for the next Register Access</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regvalue </td>
<td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> remote_wakeup </td>
<td> On read, shows the status of Remote Wakeup. On write, initiates a remote
wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
Wakeup signalling bit in the Device Control Register is set for 1
milli-second.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regdump </td>
<td> Dumps the contents of core registers.</td>
<td> Read</td>
</tr>
<tr>
<td> hcddump </td>
<td> Dumps the current HCD state.</td>
<td> Read</td>
</tr>
<tr>
<td> hcd_frrem </td>
<td> Shows the average value of the Frame Remaining
field in the Host Frame Number/Frame Remaining register when an SOF interrupt
occurs. This can be used to determine the average interrupt latency. Also
shows the average Frame Remaining value for start_transfer and the "a" and
"b" sample points. The "a" and "b" sample points may be used during debugging
bto determine how long it takes to execute a section of the HCD code.</td>
<td> Read</td>
</tr>
<tr>
<td> rd_reg_test </td>
<td> Displays the time required to read the GNPTXFSIZ register many times
(the output shows the number of times the register is read).
<td> Read</td>
</tr>
<tr>
<td> wr_reg_test </td>
<td> Displays the time required to write the GNPTXFSIZ register many times
(the output shows the number of times the register is written).
<td> Read</td>
</tr>
</table>
Example usage:
To get the current mode:
cat /sys/devices/lm0/mode
To power down the USB:
echo 0 > /sys/devices/lm0/buspower
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/stat.h> /* permission constants */
#include <asm/io.h>
#include "dwc_otg_plat.h"
#include "dwc_otg_attr.h"
#include "dwc_otg_driver.h"
// #include "dwc_otg_pcd.h"
#include "dwc_otg_hcd.h"
// 20070316, winder added.
#ifndef SZ_256K
#define SZ_256K 0x00040000
#endif
/*
* MACROs for defining sysfs attribute
*/
#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val; \
val = dwc_read_reg32 (_addr_); \
val = (val & (_mask_)) >> _shift_; \
return sprintf (buf, "%s = 0x%x\n", _string_, val); \
}
#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t set = simple_strtoul(buf, NULL, 16); \
uint32_t clear = set; \
clear = ((~clear) << _shift_) & _mask_; \
set = (set << _shift_) & _mask_; \
dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
dwc_modify_reg32(_addr_, clear, set); \
return count; \
}
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
/*
* MACROs for defining sysfs attribute for 32-bit registers
*/
#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val; \
val = dwc_read_reg32 (_addr_); \
return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
}
#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val = simple_strtoul(buf, NULL, 16); \
dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
dwc_write_reg32(_addr_, val); \
return count; \
}
#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
/** @name Functions for Show/Store of Attributes */
/**@{*/
/**
* Show the register offset of the Register Access.
*/
static ssize_t regoffset_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
}
/**
* Set the register offset for the next Register Access Read/Write
*/
static ssize_t regoffset_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t offset = simple_strtoul(buf, NULL, 16);
//dev_dbg(_dev, "Offset=0x%08x\n", offset);
if (offset < SZ_256K ) {
otg_dev->reg_offset = offset;
}
else {
dev_err( _dev, "invalid offset\n" );
}
return count;
}
DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, regoffset_show, regoffset_store);
/**
* Show the value of the register at the offset in the reg_offset
* attribute.
*/
static ssize_t regvalue_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t val;
volatile uint32_t *addr;
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t*)(otg_dev->reg_offset +
(uint8_t*)otg_dev->base);
//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
val = dwc_read_reg32( addr );
return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
"Reg@0x%06x = 0x%08x\n",
otg_dev->reg_offset, val);
}
else {
dev_err(_dev, "Invalid offset (0x%0x)\n",
otg_dev->reg_offset);
return sprintf(buf, "invalid offset\n" );
}
}
/**
* Store the value in the register at the offset in the reg_offset
* attribute.
*
*/
static ssize_t regvalue_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
volatile uint32_t * addr;
uint32_t val = simple_strtoul(buf, NULL, 16);
//dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t*)(otg_dev->reg_offset +
(uint8_t*)otg_dev->base);
//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
dwc_write_reg32( addr, val );
}
else {
dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
otg_dev->reg_offset);
}
return count;
}
DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
/*
* Attributes
*/
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
/**
* @todo Add code to initiate the HNP.
*/
/**
* Show the HNP status bit
*/
static ssize_t hnp_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
gotgctl_data_t val;
val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
}
/**
* Set the HNP Request bit
*/
static ssize_t hnp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t in = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
gotgctl_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.hnpreq = in;
dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
/**
* @todo Add code to initiate the SRP.
*/
/**
* Show the SRP status bit
*/
static ssize_t srp_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
gotgctl_data_t val;
val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
#else
return sprintf(buf, "Host Only Mode!\n");
#endif
}
/**
* Set the SRP Request bit
*/
static ssize_t srp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_pcd_initiate_srp(otg_dev->pcd);
#endif
return count;
}
DEVICE_ATTR(srp, 0644, srp_show, srp_store);
/**
* @todo Need to do more for power on/off?
*/
/**
* Show the Bus Power status
*/
static ssize_t buspower_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
hprt0_data_t val;
val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
}
/**
* Set the Bus Power status
*/
static ssize_t buspower_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t on = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
hprt0_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.prtpwr = on;
//dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
/**
* @todo Need to do more for suspend?
*/
/**
* Show the Bus Suspend status
*/
static ssize_t bussuspend_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
hprt0_data_t val;
val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
}
/**
* Set the Bus Suspend status
*/
static ssize_t bussuspend_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t in = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
hprt0_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.prtsusp = in;
dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
/**
* Show the status of Remote Wakeup.
*/
static ssize_t remote_wakeup_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dctl_data_t val;
val.d32 = dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
#else
return sprintf(buf, "Host Only Mode!\n");
#endif
}
/**
* Initiate a remote wakeup of the host. The Device control register
* Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
* flag is set.
*
*/
static ssize_t remote_wakeup_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
#ifndef DWC_HOST_ONLY
uint32_t val = simple_strtoul(buf, NULL, 16);
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
if (val&1) {
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
}
else {
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
}
#endif
return count;
}
DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
remote_wakeup_store);
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifdef DEBUG
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev);
dwc_otg_dump_global_registers( otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if)) {
dwc_otg_dump_host_registers( otg_dev->core_if);
} else {
dwc_otg_dump_dev_registers( otg_dev->core_if);
}
#endif
return sprintf( buf, "Register Dump\n" );
}
DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
/**
* Dump the current hcd state.
*/
static ssize_t hcddump_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_hcd_dump_state(otg_dev->hcd);
#endif
return sprintf( buf, "HCD Dump\n" );
}
DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
*/
static ssize_t hcd_frrem_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_hcd_dump_frrem(otg_dev->hcd);
#endif
return sprintf( buf, "HCD Dump Frame Remaining\n" );
}
DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
/**
* Displays the time required to read the GNPTXFSIZ register many times (the
* output shows the number of times the register is read).
*/
#define RW_REG_COUNT 10000000
#define MSEC_PER_JIFFIE 1000/HZ
static ssize_t rd_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
int i;
int time;
int start_jiffies;
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++) {
dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
}
time = jiffies - start_jiffies;
return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
}
DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
/**
* Displays the time required to write the GNPTXFSIZ register many times (the
* output shows the number of times the register is written).
*/
static ssize_t wr_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
int i;
int time;
int start_jiffies;
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t reg_val;
printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++) {
dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
}
time = jiffies - start_jiffies;
return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
}
DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
/**@}*/
/**
* Create the device files
*/
void dwc_otg_attr_create (struct device *_dev)
{
int retval;
retval = device_create_file(_dev, &dev_attr_regoffset);
retval += device_create_file(_dev, &dev_attr_regvalue);
retval += device_create_file(_dev, &dev_attr_mode);
retval += device_create_file(_dev, &dev_attr_hnpcapable);
retval += device_create_file(_dev, &dev_attr_srpcapable);
retval += device_create_file(_dev, &dev_attr_hnp);
retval += device_create_file(_dev, &dev_attr_srp);
retval += device_create_file(_dev, &dev_attr_buspower);
retval += device_create_file(_dev, &dev_attr_bussuspend);
retval += device_create_file(_dev, &dev_attr_busconnected);
retval += device_create_file(_dev, &dev_attr_gotgctl);
retval += device_create_file(_dev, &dev_attr_gusbcfg);
retval += device_create_file(_dev, &dev_attr_grxfsiz);
retval += device_create_file(_dev, &dev_attr_gnptxfsiz);
retval += device_create_file(_dev, &dev_attr_gpvndctl);
retval += device_create_file(_dev, &dev_attr_ggpio);
retval += device_create_file(_dev, &dev_attr_guid);
retval += device_create_file(_dev, &dev_attr_gsnpsid);
retval += device_create_file(_dev, &dev_attr_devspeed);
retval += device_create_file(_dev, &dev_attr_enumspeed);
retval += device_create_file(_dev, &dev_attr_hptxfsiz);
retval += device_create_file(_dev, &dev_attr_hprt0);
retval += device_create_file(_dev, &dev_attr_remote_wakeup);
retval += device_create_file(_dev, &dev_attr_regdump);
retval += device_create_file(_dev, &dev_attr_hcddump);
retval += device_create_file(_dev, &dev_attr_hcd_frrem);
retval += device_create_file(_dev, &dev_attr_rd_reg_test);
retval += device_create_file(_dev, &dev_attr_wr_reg_test);
if(retval != 0)
{
DWC_PRINT("cannot create sysfs device files.\n");
// DWC_PRINT("killing own sysfs device files!\n");
dwc_otg_attr_remove(_dev);
}
}
/**
* Remove the device files
*/
void dwc_otg_attr_remove (struct device *_dev)
{
device_remove_file(_dev, &dev_attr_regoffset);
device_remove_file(_dev, &dev_attr_regvalue);
device_remove_file(_dev, &dev_attr_mode);
device_remove_file(_dev, &dev_attr_hnpcapable);
device_remove_file(_dev, &dev_attr_srpcapable);
device_remove_file(_dev, &dev_attr_hnp);
device_remove_file(_dev, &dev_attr_srp);
device_remove_file(_dev, &dev_attr_buspower);
device_remove_file(_dev, &dev_attr_bussuspend);
device_remove_file(_dev, &dev_attr_busconnected);
device_remove_file(_dev, &dev_attr_gotgctl);
device_remove_file(_dev, &dev_attr_gusbcfg);
device_remove_file(_dev, &dev_attr_grxfsiz);
device_remove_file(_dev, &dev_attr_gnptxfsiz);
device_remove_file(_dev, &dev_attr_gpvndctl);
device_remove_file(_dev, &dev_attr_ggpio);
device_remove_file(_dev, &dev_attr_guid);
device_remove_file(_dev, &dev_attr_gsnpsid);
device_remove_file(_dev, &dev_attr_devspeed);
device_remove_file(_dev, &dev_attr_enumspeed);
device_remove_file(_dev, &dev_attr_hptxfsiz);
device_remove_file(_dev, &dev_attr_hprt0);
device_remove_file(_dev, &dev_attr_remote_wakeup);
device_remove_file(_dev, &dev_attr_regdump);
device_remove_file(_dev, &dev_attr_hcddump);
device_remove_file(_dev, &dev_attr_hcd_frrem);
device_remove_file(_dev, &dev_attr_rd_reg_test);
device_remove_file(_dev, &dev_attr_wr_reg_test);
}

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510275 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_ATTR_H__)
#define __DWC_OTG_ATTR_H__
/** @file
* This file contains the interface to the Linux device attributes.
*/
extern struct device_attribute dev_attr_regoffset;
extern struct device_attribute dev_attr_regvalue;
extern struct device_attribute dev_attr_mode;
extern struct device_attribute dev_attr_hnpcapable;
extern struct device_attribute dev_attr_srpcapable;
extern struct device_attribute dev_attr_hnp;
extern struct device_attribute dev_attr_srp;
extern struct device_attribute dev_attr_buspower;
extern struct device_attribute dev_attr_bussuspend;
extern struct device_attribute dev_attr_busconnected;
extern struct device_attribute dev_attr_gotgctl;
extern struct device_attribute dev_attr_gusbcfg;
extern struct device_attribute dev_attr_grxfsiz;
extern struct device_attribute dev_attr_gnptxfsiz;
extern struct device_attribute dev_attr_gpvndctl;
extern struct device_attribute dev_attr_ggpio;
extern struct device_attribute dev_attr_guid;
extern struct device_attribute dev_attr_gsnpsid;
extern struct device_attribute dev_attr_devspeed;
extern struct device_attribute dev_attr_enumspeed;
extern struct device_attribute dev_attr_hptxfsiz;
extern struct device_attribute dev_attr_hprt0;
void dwc_otg_attr_create (struct device *_dev);
void dwc_otg_attr_remove (struct device *_dev);
#endif

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 631780 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_CIL_H__)
#define __DWC_CIL_H__
#include "dwc_otg_plat.h"
#include "dwc_otg_regs.h"
#ifdef DEBUG
#include "linux/timer.h"
#endif
/* the OTG capabilities. */
#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
/* the maximum speed of operation in host and device mode. */
#define DWC_SPEED_PARAM_HIGH 0
#define DWC_SPEED_PARAM_FULL 1
/* the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. */
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
/* the type of PHY interface to use. */
#define DWC_PHY_TYPE_PARAM_FS 0
#define DWC_PHY_TYPE_PARAM_UTMI 1
#define DWC_PHY_TYPE_PARAM_ULPI 2
/* whether to use the internal or external supply to
* drive the vbus with a ULPI phy. */
#define DWC_PHY_ULPI_INTERNAL_VBUS 0
#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
/* EP type. */
/**
* @file
* This file contains the interface to the Core Interface Layer.
*/
/**
* The <code>dwc_ep</code> structure represents the state of a single
* endpoint when acting in device mode. It contains the data items
* needed for an endpoint to be activated and transfer packets.
*/
typedef struct dwc_ep {
/** EP number used for register address lookup */
uint8_t num;
/** EP direction 0 = OUT */
unsigned is_in : 1;
/** EP active. */
unsigned active : 1;
/** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
unsigned tx_fifo_num : 4;
/** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
unsigned type : 2;
#define DWC_OTG_EP_TYPE_CONTROL 0
#define DWC_OTG_EP_TYPE_ISOC 1
#define DWC_OTG_EP_TYPE_BULK 2
#define DWC_OTG_EP_TYPE_INTR 3
/** DATA start PID for INTR and BULK EP */
unsigned data_pid_start : 1;
/** Frame (even/odd) for ISOC EP */
unsigned even_odd_frame : 1;
/** Max Packet bytes */
unsigned maxpacket : 11;
/** @name Transfer state */
/** @{ */
/**
* Pointer to the beginning of the transfer buffer -- do not modify
* during transfer.
*/
uint32_t dma_addr;
uint8_t *start_xfer_buff;
/** pointer to the transfer buffer */
uint8_t *xfer_buff;
/** Number of bytes to transfer */
unsigned xfer_len : 19;
/** Number of bytes transferred. */
unsigned xfer_count : 19;
/** Sent ZLP */
unsigned sent_zlp : 1;
/** Total len for control transfer */
unsigned total_len : 19;
/** stall clear flag */
unsigned stall_clear_flag : 1;
/** @} */
} dwc_ep_t;
/*
* Reasons for halting a host channel.
*/
typedef enum dwc_otg_halt_status {
DWC_OTG_HC_XFER_NO_HALT_STATUS,
DWC_OTG_HC_XFER_COMPLETE,
DWC_OTG_HC_XFER_URB_COMPLETE,
DWC_OTG_HC_XFER_ACK,
DWC_OTG_HC_XFER_NAK,
DWC_OTG_HC_XFER_NYET,
DWC_OTG_HC_XFER_STALL,
DWC_OTG_HC_XFER_XACT_ERR,
DWC_OTG_HC_XFER_FRAME_OVERRUN,
DWC_OTG_HC_XFER_BABBLE_ERR,
DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
DWC_OTG_HC_XFER_AHB_ERR,
DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
DWC_OTG_HC_XFER_URB_DEQUEUE
} dwc_otg_halt_status_e;
/**
* Host channel descriptor. This structure represents the state of a single
* host channel when acting in host mode. It contains the data items needed to
* transfer packets to an endpoint via a host channel.
*/
typedef struct dwc_hc {
/** Host channel number used for register address lookup */
uint8_t hc_num;
/** Device to access */
unsigned dev_addr : 7;
/** EP to access */
unsigned ep_num : 4;
/** EP direction. 0: OUT, 1: IN */
unsigned ep_is_in : 1;
/**
* EP speed.
* One of the following values:
* - DWC_OTG_EP_SPEED_LOW
* - DWC_OTG_EP_SPEED_FULL
* - DWC_OTG_EP_SPEED_HIGH
*/
unsigned speed : 2;
#define DWC_OTG_EP_SPEED_LOW 0
#define DWC_OTG_EP_SPEED_FULL 1
#define DWC_OTG_EP_SPEED_HIGH 2
/**
* Endpoint type.
* One of the following values:
* - DWC_OTG_EP_TYPE_CONTROL: 0
* - DWC_OTG_EP_TYPE_ISOC: 1
* - DWC_OTG_EP_TYPE_BULK: 2
* - DWC_OTG_EP_TYPE_INTR: 3
*/
unsigned ep_type : 2;
/** Max packet size in bytes */
unsigned max_packet : 11;
/**
* PID for initial transaction.
* 0: DATA0,<br>
* 1: DATA2,<br>
* 2: DATA1,<br>
* 3: MDATA (non-Control EP),
* SETUP (Control EP)
*/
unsigned data_pid_start : 2;
#define DWC_OTG_HC_PID_DATA0 0
#define DWC_OTG_HC_PID_DATA2 1
#define DWC_OTG_HC_PID_DATA1 2
#define DWC_OTG_HC_PID_MDATA 3
#define DWC_OTG_HC_PID_SETUP 3
/** Number of periodic transactions per (micro)frame */
unsigned multi_count: 2;
/** @name Transfer State */
/** @{ */
/** Pointer to the current transfer buffer position. */
uint8_t *xfer_buff;
/** Total number of bytes to transfer. */
uint32_t xfer_len;
/** Number of bytes transferred so far. */
uint32_t xfer_count;
/** Packet count at start of transfer.*/
uint16_t start_pkt_count;
/**
* Flag to indicate whether the transfer has been started. Set to 1 if
* it has been started, 0 otherwise.
*/
uint8_t xfer_started;
/**
* Set to 1 to indicate that a PING request should be issued on this
* channel. If 0, process normally.
*/
uint8_t do_ping;
/**
* Set to 1 to indicate that the error count for this transaction is
* non-zero. Set to 0 if the error count is 0.
*/
uint8_t error_state;
/**
* Set to 1 to indicate that this channel should be halted the next
* time a request is queued for the channel. This is necessary in
* slave mode if no request queue space is available when an attempt
* is made to halt the channel.
*/
uint8_t halt_on_queue;
/**
* Set to 1 if the host channel has been halted, but the core is not
* finished flushing queued requests. Otherwise 0.
*/
uint8_t halt_pending;
/**
* Reason for halting the host channel.
*/
dwc_otg_halt_status_e halt_status;
/*
* Split settings for the host channel
*/
uint8_t do_split; /**< Enable split for the channel */
uint8_t complete_split; /**< Enable complete split */
uint8_t hub_addr; /**< Address of high speed hub */
uint8_t port_addr; /**< Port of the low/full speed device */
/** Split transaction position
* One of the following values:
* - DWC_HCSPLIT_XACTPOS_MID
* - DWC_HCSPLIT_XACTPOS_BEGIN
* - DWC_HCSPLIT_XACTPOS_END
* - DWC_HCSPLIT_XACTPOS_ALL */
uint8_t xact_pos;
/** Set when the host channel does a short read. */
uint8_t short_read;
/**
* Number of requests issued for this channel since it was assigned to
* the current transfer (not counting PINGs).
*/
uint8_t requests;
/**
* Queue Head for the transfer being processed by this channel.
*/
struct dwc_otg_qh *qh;
/** @} */
/** Entry in list of host channels. */
struct list_head hc_list_entry;
} dwc_hc_t;
/**
* The following parameters may be specified when starting the module. These
* parameters define how the DWC_otg controller should be configured.
* Parameter values are passed to the CIL initialization function
* dwc_otg_cil_init.
*/
typedef struct dwc_otg_core_params
{
int32_t opt;
//#define dwc_param_opt_default 1
/**
* Specifies the OTG capabilities. The driver will automatically
* detect the value for this parameter if none is specified.
* 0 - HNP and SRP capable (default)
* 1 - SRP Only capable
* 2 - No HNP/SRP capable
*/
int32_t otg_cap;
#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
/**
* Specifies whether to use slave or DMA mode for accessing the data
* FIFOs. The driver will automatically detect the value for this
* parameter if none is specified.
* 0 - Slave
* 1 - DMA (default, if available)
*/
int32_t dma_enable;
//#define dwc_param_dma_enable_default 1
/** The DMA Burst size (applicable only for External DMA
* Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
*/
int32_t dma_burst_size; /* Translate this to GAHBCFG values */
//#define dwc_param_dma_burst_size_default 32
/**
* Specifies the maximum speed of operation in host and device mode.
* The actual speed depends on the speed of the attached device and
* the value of phy_type. The actual speed depends on the speed of the
* attached device.
* 0 - High Speed (default)
* 1 - Full Speed
*/
int32_t speed;
//#define dwc_param_speed_default 0
#define DWC_SPEED_PARAM_HIGH 0
#define DWC_SPEED_PARAM_FULL 1
/** Specifies whether low power mode is supported when attached
* to a Full Speed or Low Speed device in host mode.
* 0 - Don't support low power mode (default)
* 1 - Support low power mode
*/
int32_t host_support_fs_ls_low_power;
//#define dwc_param_host_support_fs_ls_low_power_default 0
/** Specifies the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. This parameter is applicable only if
* HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
* then defaults to 6 MHZ otherwise 48 MHZ.
*
* 0 - 48 MHz
* 1 - 6 MHz
*/
int32_t host_ls_low_power_phy_clk;
//#define dwc_param_host_ls_low_power_phy_clk_default 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
/**
* 0 - Use cC FIFO size parameters
* 1 - Allow dynamic FIFO sizing (default)
*/
int32_t enable_dynamic_fifo;
//#define dwc_param_enable_dynamic_fifo_default 1
/** Total number of 4-byte words in the data FIFO memory. This
* memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
* Tx FIFOs.
* 32 to 32768 (default 8192)
* Note: The total FIFO memory depth in the FPGA configuration is 8192.
*/
int32_t data_fifo_size;
//#define dwc_param_data_fifo_size_default 8192
/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1064)
*/
int32_t dev_rx_fifo_size;
//#define dwc_param_dev_rx_fifo_size_default 1064
/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
* when dynamic FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t dev_nperio_tx_fifo_size;
//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in each of the periodic Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
//#define dwc_param_dev_perio_tx_fifo_size_default 256
/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t host_rx_fifo_size;
//#define dwc_param_host_rx_fifo_size_default 1024
/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
* when Dynamic FIFO sizing is enabled in the core.
* 16 to 32768 (default 1024)
*/
int32_t host_nperio_tx_fifo_size;
//#define dwc_param_host_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t host_perio_tx_fifo_size;
//#define dwc_param_host_perio_tx_fifo_size_default 1024
/** The maximum transfer size supported in bytes.
* 2047 to 65,535 (default 65,535)
*/
int32_t max_transfer_size;
//#define dwc_param_max_transfer_size_default 65535
/** The maximum number of packets in a transfer.
* 15 to 511 (default 511)
*/
int32_t max_packet_count;
//#define dwc_param_max_packet_count_default 511
/** The number of host channel registers to use.
* 1 to 16 (default 12)
* Note: The FPGA configuration supports a maximum of 12 host channels.
*/
int32_t host_channels;
//#define dwc_param_host_channels_default 12
/** The number of endpoints in addition to EP0 available for device
* mode operations.
* 1 to 15 (default 6 IN and OUT)
* Note: The FPGA configuration supports a maximum of 6 IN and OUT
* endpoints in addition to EP0.
*/
int32_t dev_endpoints;
//#define dwc_param_dev_endpoints_default 6
/**
* Specifies the type of PHY interface to use. By default, the driver
* will automatically detect the phy_type.
*
* 0 - Full Speed PHY
* 1 - UTMI+ (default)
* 2 - ULPI
*/
int32_t phy_type;
#define DWC_PHY_TYPE_PARAM_FS 0
#define DWC_PHY_TYPE_PARAM_UTMI 1
#define DWC_PHY_TYPE_PARAM_ULPI 2
//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
/**
* Specifies the UTMI+ Data Width. This parameter is
* applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
* PHY_TYPE, this parameter indicates the data width between
* the MAC and the ULPI Wrapper.) Also, this parameter is
* applicable only if the OTG_HSPHY_WIDTH cC parameter was set
* to "8 and 16 bits", meaning that the core has been
* configured to work at either data path width.
*
* 8 or 16 bits (default 16)
*/
int32_t phy_utmi_width;
//#define dwc_param_phy_utmi_width_default 16
/**
* Specifies whether the ULPI operates at double or single
* data rate. This parameter is only applicable if PHY_TYPE is
* ULPI.
*
* 0 - single data rate ULPI interface with 8 bit wide data
* bus (default)
* 1 - double data rate ULPI interface with 4 bit wide data
* bus
*/
int32_t phy_ulpi_ddr;
//#define dwc_param_phy_ulpi_ddr_default 0
/**
* Specifies whether to use the internal or external supply to
* drive the vbus with a ULPI phy.
*/
int32_t phy_ulpi_ext_vbus;
#define DWC_PHY_ULPI_INTERNAL_VBUS 0
#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
/**
* Specifies whether to use the I2Cinterface for full speed PHY. This
* parameter is only applicable if PHY_TYPE is FS.
* 0 - No (default)
* 1 - Yes
*/
int32_t i2c_enable;
//#define dwc_param_i2c_enable_default 0
int32_t ulpi_fs_ls;
//#define dwc_param_ulpi_fs_ls_default 0
int32_t ts_dline;
//#define dwc_param_ts_dline_default 0
/**
* Specifies whether dedicated transmit FIFOs are
* enabled for non periodic IN endpoints in device mode
* 0 - No
* 1 - Yes
*/
int32_t en_multiple_tx_fifo;
#define dwc_param_en_multiple_tx_fifo_default 1
/** Number of 4-byte words in each of the Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
#define dwc_param_dev_tx_fifo_size_default 256
/** Thresholding enable flag-
* bit 0 - enable non-ISO Tx thresholding
* bit 1 - enable ISO Tx thresholding
* bit 2 - enable Rx thresholding
*/
uint32_t thr_ctl;
#define dwc_param_thr_ctl_default 0
/** Thresholding length for Tx
* FIFOs in 32 bit DWORDs
*/
uint32_t tx_thr_length;
#define dwc_param_tx_thr_length_default 64
/** Thresholding length for Rx
* FIFOs in 32 bit DWORDs
*/
uint32_t rx_thr_length;
#define dwc_param_rx_thr_length_default 64
} dwc_otg_core_params_t;
#ifdef DEBUG
struct dwc_otg_core_if;
typedef struct hc_xfer_info
{
struct dwc_otg_core_if *core_if;
dwc_hc_t *hc;
} hc_xfer_info_t;
#endif
/**
* The <code>dwc_otg_core_if</code> structure contains information needed to manage
* the DWC_otg controller acting in either host or device mode. It
* represents the programming view of the controller as a whole.
*/
typedef struct dwc_otg_core_if
{
/** Parameters that define how the core should be configured.*/
dwc_otg_core_params_t *core_params;
/** Core Global registers starting at offset 000h. */
dwc_otg_core_global_regs_t *core_global_regs;
/** Device-specific information */
dwc_otg_dev_if_t *dev_if;
/** Host-specific information */
dwc_otg_host_if_t *host_if;
/*
* Set to 1 if the core PHY interface bits in USBCFG have been
* initialized.
*/
uint8_t phy_init_done;
/*
* SRP Success flag, set by srp success interrupt in FS I2C mode
*/
uint8_t srp_success;
uint8_t srp_timer_started;
/* Common configuration information */
/** Power and Clock Gating Control Register */
volatile uint32_t *pcgcctl;
#define DWC_OTG_PCGCCTL_OFFSET 0xE00
/** Push/pop addresses for endpoints or host channels.*/
uint32_t *data_fifo[MAX_EPS_CHANNELS];
#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
#define DWC_OTG_DATA_FIFO_SIZE 0x1000
/** Total RAM for FIFOs (Bytes) */
uint16_t total_fifo_size;
/** Size of Rx FIFO (Bytes) */
uint16_t rx_fifo_size;
/** Size of Non-periodic Tx FIFO (Bytes) */
uint16_t nperio_tx_fifo_size;
/** 1 if DMA is enabled, 0 otherwise. */
uint8_t dma_enable;
/** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
uint8_t en_multiple_tx_fifo;
/** Set to 1 if multiple packets of a high-bandwidth transfer is in
* process of being queued */
uint8_t queuing_high_bandwidth;
/** Hardware Configuration -- stored here for convenience.*/
hwcfg1_data_t hwcfg1;
hwcfg2_data_t hwcfg2;
hwcfg3_data_t hwcfg3;
hwcfg4_data_t hwcfg4;
/** The operational State, during transations
* (a_host>>a_peripherial and b_device=>b_host) this may not
* match the core but allows the software to determine
* transitions.
*/
uint8_t op_state;
/**
* Set to 1 if the HCD needs to be restarted on a session request
* interrupt. This is required if no connector ID status change has
* occurred since the HCD was last disconnected.
*/
uint8_t restart_hcd_on_session_req;
/** HCD callbacks */
/** A-Device is a_host */
#define A_HOST (1)
/** A-Device is a_suspend */
#define A_SUSPEND (2)
/** A-Device is a_peripherial */
#define A_PERIPHERAL (3)
/** B-Device is operating as a Peripheral. */
#define B_PERIPHERAL (4)
/** B-Device is operating as a Host. */
#define B_HOST (5)
/** HCD callbacks */
struct dwc_otg_cil_callbacks *hcd_cb;
/** PCD callbacks */
struct dwc_otg_cil_callbacks *pcd_cb;
/** Device mode Periodic Tx FIFO Mask */
uint32_t p_tx_msk;
/** Device mode Periodic Tx FIFO Mask */
uint32_t tx_msk;
#ifdef DEBUG
uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
#if 1 // winder
uint32_t hfnum_7_samples;
uint32_t hfnum_7_frrem_accum;
uint32_t hfnum_0_samples;
uint32_t hfnum_0_frrem_accum;
uint32_t hfnum_other_samples;
uint32_t hfnum_other_frrem_accum;
#else
uint32_t hfnum_7_samples;
uint64_t hfnum_7_frrem_accum;
uint32_t hfnum_0_samples;
uint64_t hfnum_0_frrem_accum;
uint32_t hfnum_other_samples;
uint64_t hfnum_other_frrem_accum;
#endif
resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */
#endif
} dwc_otg_core_if_t;
/*
* The following functions support initialization of the CIL driver component
* and the DWC_otg controller.
*/
extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
dwc_otg_core_params_t *_core_params);
extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
/** @name Device CIL Functions
* The following functions support managing the DWC_otg controller in device
* mode.
*/
/**@{*/
extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
/**@}*/
/** @name Host CIL Functions
* The following functions support managing the DWC_otg controller in host
* mode.
*/
/**@{*/
extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
dwc_hc_t *_hc,
dwc_otg_halt_status_e _halt_status);
extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
/**
* This function Reads HPRT0 in preparation to modify. It keeps the
* WC bits 0 so that if they are read as 1, they won't clear when you
* write it back
*/
static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
{
hprt0_data_t hprt0;
hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
hprt0.b.prtena = 0;
hprt0.b.prtconndet = 0;
hprt0.b.prtenchng = 0;
hprt0.b.prtovrcurrchng = 0;
return hprt0.d32;
}
extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
/**@}*/
/** @name Common CIL Functions
* The following functions support managing the DWC_otg controller in either
* device or host mode.
*/
/**@{*/
extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
uint8_t *dest,
uint16_t bytes);
extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
const int _num );
extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
#define NP_TXFIFO_EMPTY -1
#define MAX_NP_TXREQUEST_Q_SLOTS 8
/**
* This function returns the endpoint number of the request at
* the top of non-periodic TX FIFO, or -1 if the request FIFO is
* empty.
*/
static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) {
gnptxsts_data_t txstatus = {.d32 = 0};
txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ?
-1 : txstatus.b.nptxqtop_chnep);
}
/**
* This function returns the Core Interrupt register.
*/
static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
}
/**
* This function returns the OTG Interrupt register.
*/
static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
}
/**
* This function reads the Device All Endpoints Interrupt register and
* returns the IN endpoint interrupt bits.
*/
static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) {
uint32_t v;
v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
return (v & 0xffff);
}
/**
* This function reads the Device All Endpoints Interrupt register and
* returns the OUT endpoint interrupt bits.
*/
static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) {
uint32_t v;
v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
return ((v & 0xffff0000) >> 16);
}
/**
* This function returns the Device IN EP Interrupt register
*/
static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if,
dwc_ep_t *_ep)
{
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v, msk, emp;
msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
msk |= ((emp >> _ep->num) & 0x1) << 7;
v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk;
/*
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v;
v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) &
dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
*/
return v;
}
/**
* This function returns the Device OUT EP Interrupt register
*/
static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
dwc_ep_t *_ep)
{
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v;
v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) &
dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
return v;
}
/**
* This function returns the Host All Channel Interrupt register
*/
static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
{
return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
}
static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
{
return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
}
/**
* This function returns the mode of the operation, host or device.
*
* @return 0 - Device Mode, 1 - Host Mode
*/
static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
}
static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
{
return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
}
static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
{
return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
}
extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
/**@}*/
/**
* DWC_otg CIL callback structure. This structure allows the HCD and
* PCD to register functions used for starting and stopping the PCD
* and HCD for role change on for a DRD.
*/
typedef struct dwc_otg_cil_callbacks
{
/** Start function for role change */
int (*start) (void *_p);
/** Stop Function for role change */
int (*stop) (void *_p);
/** Disconnect Function for role change */
int (*disconnect) (void *_p);
/** Resume/Remote wakeup Function */
int (*resume_wakeup) (void *_p);
/** Suspend function */
int (*suspend) (void *_p);
/** Session Start (SRP) */
int (*session_start) (void *_p);
/** Pointer passed to start() and stop() */
void *p;
} dwc_otg_cil_callbacks_t;
extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
dwc_otg_cil_callbacks_t *_cb,
void *_p);
extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
dwc_otg_cil_callbacks_t *_cb,
void *_p);
#endif

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/******************************************************************************
**
** FILE NAME : dwc_otg_cil_ifx.h
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 07 Sep. 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Default param value.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 April 2007 Sung Winder Initiate Version
*******************************************************************************/
#if !defined(__DWC_OTG_CIL_IFX_H__)
#define __DWC_OTG_CIL_IFX_H__
/* ================ Default param value ================== */
#define dwc_param_opt_default 1
#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
#define dwc_param_dma_enable_default 1
#define dwc_param_dma_burst_size_default 32
#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH
#define dwc_param_host_support_fs_ls_low_power_default 0
#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ
#define dwc_param_enable_dynamic_fifo_default 1
#define dwc_param_data_fifo_size_default 2048
#define dwc_param_dev_rx_fifo_size_default 1024
#define dwc_param_dev_nperio_tx_fifo_size_default 1024
#define dwc_param_dev_perio_tx_fifo_size_default 768
#define dwc_param_host_rx_fifo_size_default 640
#define dwc_param_host_nperio_tx_fifo_size_default 640
#define dwc_param_host_perio_tx_fifo_size_default 768
#define dwc_param_max_transfer_size_default 65535
#define dwc_param_max_packet_count_default 511
#define dwc_param_host_channels_default 16
#define dwc_param_dev_endpoints_default 6
#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
#define dwc_param_phy_utmi_width_default 16
#define dwc_param_phy_ulpi_ddr_default 0
#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
#define dwc_param_i2c_enable_default 0
#define dwc_param_ulpi_fs_ls_default 0
#define dwc_param_ts_dline_default 0
/* ======================================================= */
#endif // __DWC_OTG_CIL_IFX_H__

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil_intr.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 553126 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
/** @file
*
* The Core Interface Layer provides basic services for accessing and
* managing the DWC_otg hardware. These services are used by both the
* Host Controller Driver and the Peripheral Controller Driver.
*
* This file contains the Common Interrupt handlers.
*/
#include "dwc_otg_plat.h"
#include "dwc_otg_regs.h"
#include "dwc_otg_cil.h"
#ifdef DEBUG
inline const char *op_state_str( dwc_otg_core_if_t *_core_if )
{
return (_core_if->op_state==A_HOST?"a_host":
(_core_if->op_state==A_SUSPEND?"a_suspend":
(_core_if->op_state==A_PERIPHERAL?"a_peripheral":
(_core_if->op_state==B_PERIPHERAL?"b_peripheral":
(_core_if->op_state==B_HOST?"b_host":
"unknown")))));
}
#endif
/** This function will log a debug message
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
dwc_otg_mode(_core_if) ? "Host" : "Device");
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.modemismatch = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/** Start the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
_core_if->hcd_cb->start( _core_if->hcd_cb->p );
}
}
/** Stop the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_stop( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
_core_if->hcd_cb->stop( _core_if->hcd_cb->p );
}
}
/** Disconnect the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_disconnect( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
_core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
}
}
/** Inform the HCD the a New Session has begun. Helper function for
* using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_session_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->session_start) {
_core_if->hcd_cb->session_start( _core_if->hcd_cb->p );
}
}
/** Start the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->start ) {
_core_if->pcd_cb->start( _core_if->pcd_cb->p );
}
}
/** Stop the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_stop( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->stop ) {
_core_if->pcd_cb->stop( _core_if->pcd_cb->p );
}
}
/** Suspend the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_suspend( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->suspend ) {
_core_if->pcd_cb->suspend( _core_if->pcd_cb->p );
}
}
/** Resume the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_resume( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup ) {
_core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
}
}
/**
* This function handles the OTG Interrupts. It reads the OTG
* Interrupt Register (GOTGINT) to determine what interrupt has
* occurred.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *_core_if)
{
dwc_otg_core_global_regs_t *global_regs =
_core_if->core_global_regs;
gotgint_data_t gotgint;
gotgctl_data_t gotgctl;
gintmsk_data_t gintmsk;
gotgint.d32 = dwc_read_reg32( &global_regs->gotgint);
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
op_state_str(_core_if));
//DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32 );
if (gotgint.b.sesenddet) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Session End Detected++ (%s)\n",
op_state_str(_core_if));
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
if (_core_if->op_state == B_HOST) {
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else {
/* If not B_HOST and Device HNP still set. HNP
* Did not succeed!*/
if (gotgctl.b.devhnpen) {
DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
DWC_ERROR( "Device Not Connected/Responding!\n" );
}
/* If Session End Detected the B-Cable has
* been disconnected. */
/* Reset PCD and Gadget driver to a
* clean state. */
pcd_stop(_core_if);
}
gotgctl.d32 = 0;
gotgctl.b.devhnpen = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
}
if (gotgint.b.sesreqsucstschng) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Session Reqeust Success Status Change++\n");
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
if (gotgctl.b.sesreqscs) {
if ((_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
(_core_if->core_params->i2c_enable)) {
_core_if->srp_success = 1;
}
else {
pcd_resume( _core_if );
/* Clear Session Request */
gotgctl.d32 = 0;
gotgctl.b.sesreq = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
}
}
}
if (gotgint.b.hstnegsucstschng) {
/* Print statements during the HNP interrupt handling
* can cause it to fail.*/
gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
if (gotgctl.b.hstnegscs) {
if (dwc_otg_is_host_mode(_core_if) ) {
_core_if->op_state = B_HOST;
/*
* Need to disable SOF interrupt immediately.
* When switching from device to host, the PCD
* interrupt handler won't handle the
* interrupt if host mode is already set. The
* HCD interrupt handler won't get called if
* the HCD state is HALT. This means that the
* interrupt does not get handled and Linux
* complains loudly.
*/
gintmsk.d32 = 0;
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&global_regs->gintmsk,
gintmsk.d32, 0);
pcd_stop(_core_if);
/*
* Initialize the Core for Host mode.
*/
hcd_start( _core_if );
_core_if->op_state = B_HOST;
}
} else {
gotgctl.d32 = 0;
gotgctl.b.hnpreq = 1;
gotgctl.b.devhnpen = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
DWC_DEBUGPL( DBG_ANY, "HNP Failed\n");
DWC_ERROR( "Device Not Connected/Responding\n" );
}
}
if (gotgint.b.hstnegdet) {
/* The disconnect interrupt is set at the same time as
* Host Negotiation Detected. During the mode
* switch all interrupts are cleared so the disconnect
* interrupt handler will not get executed.
*/
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Host Negotiation Detected++ (%s)\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
if (dwc_otg_is_device_mode(_core_if)){
DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",_core_if->op_state);
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = A_PERIPHERAL;
} else {
/*
* Need to disable SOF interrupt immediately. When
* switching from device to host, the PCD interrupt
* handler won't handle the interrupt if host mode is
* already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that
* the interrupt does not get handled and Linux
* complains loudly.
*/
gintmsk.d32 = 0;
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&global_regs->gintmsk,
gintmsk.d32, 0);
pcd_stop( _core_if );
hcd_start( _core_if );
_core_if->op_state = A_HOST;
}
}
if (gotgint.b.adevtoutchng) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"A-Device Timeout Change++\n");
}
if (gotgint.b.debdone) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Debounce Done++\n");
}
/* Clear GOTGINT */
dwc_write_reg32 (&_core_if->core_global_regs->gotgint, gotgint.d32);
return 1;
}
/**
* This function handles the Connector ID Status Change Interrupt. It
* reads the OTG Interrupt Register (GOTCTL) to determine whether this
* is a Device to Host Mode transition or a Host Mode to Device
* Transition.
*
* This only occurs when the cable is connected/removed from the PHY
* connector.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *_core_if)
{
uint32_t count = 0;
gintsts_data_t gintsts = { .d32 = 0 };
gintmsk_data_t gintmsk = { .d32 = 0 };
gotgctl_data_t gotgctl = { .d32 = 0 };
/*
* Need to disable SOF interrupt immediately. If switching from device
* to host, the PCD interrupt handler won't handle the interrupt if
* host mode is already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that the interrupt does
* not get handled and Linux complains loudly.
*/
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts) {
/* Wait for switch to device mode. */
while (!dwc_otg_is_device_mode(_core_if) ){
DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
MDELAY(100);
if (++count > 10000) *(uint32_t*)NULL=0;
}
_core_if->op_state = B_PERIPHERAL;
dwc_otg_core_init(_core_if);
dwc_otg_enable_global_interrupts(_core_if);
pcd_start( _core_if );
} else {
/* A-Device connector (Host Mode) */
while (!dwc_otg_is_host_mode(_core_if) ) {
DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
MDELAY(100);
if (++count > 10000) *(uint32_t*)NULL=0;
}
_core_if->op_state = A_HOST;
/*
* Initialize the Core for Host mode.
*/
dwc_otg_core_init(_core_if);
dwc_otg_enable_global_interrupts(_core_if);
hcd_start( _core_if );
}
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device is initiating the Session
* Request Protocol to request the host to turn on bus power so a new
* session can begin. The handler responds by turning on bus power. If
* the DWC_otg controller is in low power mode, the handler brings the
* controller out of low power mode before turning on bus power.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_session_req_intr( dwc_otg_core_if_t *_core_if )
{
#ifndef DWC_HOST_ONLY // winder
hprt0_data_t hprt0;
#endif
gintsts_data_t gintsts;
#ifndef DWC_HOST_ONLY
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
if (dwc_otg_is_device_mode(_core_if) ) {
DWC_PRINT("SRP: Device mode\n");
} else {
DWC_PRINT("SRP: Host mode\n");
/* Turn on the port power bit. */
hprt0.d32 = dwc_otg_read_hprt0( _core_if );
hprt0.b.prtpwr = 1;
dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
/* Start the Connection timer. So a message can be displayed
* if connect does not occur within 10 seconds. */
hcd_session_start( _core_if );
}
#endif
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that the DWC_otg controller has detected a
* resume or remote wakeup sequence. If the DWC_otg controller is in
* low power mode, the handler must brings the controller out of low
* power mode. The controller automatically begins resume
* signaling. The handler schedules a time to stop resume signaling.
*/
int32_t dwc_otg_handle_wakeup_detected_intr( dwc_otg_core_if_t *_core_if )
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
if (dwc_otg_is_device_mode(_core_if) ) {
dctl_data_t dctl = {.d32=0};
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts));
#ifdef PARTIAL_POWER_DOWN
if (_core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32=0};
power.d32 = dwc_read_reg32( _core_if->pcgcctl );
DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
power.b.stoppclk = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.pwrclmp = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
}
#endif
/* Clear the Remote Wakeup Signalling */
dctl.b.rmtwkupsig = 1;
dwc_modify_reg32( &_core_if->dev_if->dev_global_regs->dctl,
dctl.d32, 0 );
if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) {
_core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
}
} else {
/*
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
* so that OPT tests pass with all PHYs).
*/
hprt0_data_t hprt0 = {.d32=0};
pcgcctl_data_t pcgcctl = {.d32=0};
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0);
UDELAY(10);
/* Now wait for 70 ms. */
hprt0.d32 = dwc_otg_read_hprt0( _core_if );
DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
MDELAY(70);
hprt0.b.prtres = 0; /* Resume */
dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(_core_if->host_if->hprt0));
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.wkupintr = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device has been disconnected from
* the root port.
*/
int32_t dwc_otg_handle_disconnect_intr( dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"),
op_state_str(_core_if));
/** @todo Consolidate this if statement. */
#ifndef DWC_HOST_ONLY
if (_core_if->op_state == B_HOST) {
/* If in device mode Disconnect and stop the HCD, then
* start the PCD. */
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else if (dwc_otg_is_device_mode(_core_if)) {
gotgctl_data_t gotgctl = { .d32 = 0 };
gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
if (gotgctl.b.hstsethnpen==1) {
/* Do nothing, if HNP in process the OTG
* interrupt "Host Negotiation Detected"
* interrupt will do the mode switch.
*/
} else if (gotgctl.b.devhnpen == 0) {
/* If in device mode Disconnect and stop the HCD, then
* start the PCD. */
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else {
DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
}
} else {
if (_core_if->op_state == A_HOST) {
/* A-Cable still connected but device disconnected. */
hcd_disconnect( _core_if );
}
}
#endif
/* Without OTG, we should use the disconnect function!? winder added.*/
#if 1 // NO OTG, so host only!!
hcd_disconnect( _core_if );
#endif
gintsts.d32 = 0;
gintsts.b.disconnect = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that SUSPEND state has been detected on
* the USB.
*
* For HNP the USB Suspend interrupt signals the change from
* "a_peripheral" to "a_host".
*
* When power management is enabled the core will be put in low power
* mode.
*/
int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *_core_if )
{
dsts_data_t dsts;
gintsts_data_t gintsts;
//805141:<IFTW-fchang>.removed DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
if (dwc_otg_is_device_mode( _core_if ) ) {
/* Check the Device status register to determine if the Suspend
* state is active. */
dsts.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts);
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
"HWCFG4.power Optimize=%d\n",
dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz);
#ifdef PARTIAL_POWER_DOWN
/** @todo Add a module parameter for power management. */
if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32=0};
DWC_DEBUGPL(DBG_CIL, "suspend\n");
power.b.pwrclmp = 1;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 1;
dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
power.b.stoppclk = 1;
dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
} else {
DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
}
#endif
/* PCD callback for suspend. */
pcd_suspend(_core_if);
} else {
if (_core_if->op_state == A_PERIPHERAL) {
DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
/* Clear the a_peripheral flag, back to a_host. */
pcd_stop( _core_if );
hcd_start( _core_if );
_core_if->op_state = A_HOST;
}
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.usbsuspend = 1;
dwc_write_reg32( &_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This function returns the Core Interrupt register.
*/
static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
gintmsk_data_t gintmsk;
gintmsk_data_t gintmsk_common = {.d32=0};
gintmsk_common.b.wkupintr = 1;
gintmsk_common.b.sessreqintr = 1;
gintmsk_common.b.conidstschng = 1;
gintmsk_common.b.otgintr = 1;
gintmsk_common.b.modemismatch = 1;
gintmsk_common.b.disconnect = 1;
gintmsk_common.b.usbsuspend = 1;
/** @todo: The port interrupt occurs while in device
* mode. Added code to CIL to clear the interrupt for now!
*/
gintmsk_common.b.portintr = 1;
gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts);
gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk);
#ifdef DEBUG
/* if any common interrupts set */
if (gintsts.d32 & gintmsk_common.d32) {
DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
gintsts.d32, gintmsk.d32);
}
#endif
return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
}
/**
* Common interrupt handler.
*
* The common interrupts are those that occur in both Host and Device mode.
* This handler handles the following interrupts:
* - Mode Mismatch Interrupt
* - Disconnect Interrupt
* - OTG Interrupt
* - Connector ID Status Change Interrupt
* - Session Request Interrupt.
* - Resume / Remote Wakeup Detected Interrupt.
*
*/
extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if )
{
int retval = 0;
gintsts_data_t gintsts;
gintsts.d32 = dwc_otg_read_common_intr(_core_if);
if (gintsts.b.modemismatch) {
retval |= dwc_otg_handle_mode_mismatch_intr( _core_if );
}
if (gintsts.b.otgintr) {
retval |= dwc_otg_handle_otg_intr( _core_if );
}
if (gintsts.b.conidstschng) {
retval |= dwc_otg_handle_conn_id_status_change_intr( _core_if );
}
if (gintsts.b.disconnect) {
retval |= dwc_otg_handle_disconnect_intr( _core_if );
}
if (gintsts.b.sessreqintr) {
retval |= dwc_otg_handle_session_req_intr( _core_if );
}
if (gintsts.b.wkupintr) {
retval |= dwc_otg_handle_wakeup_detected_intr( _core_if );
}
if (gintsts.b.usbsuspend) {
retval |= dwc_otg_handle_usb_suspend_intr( _core_if );
}
if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) {
/* The port interrupt occurs while in device mode with HPRT0
* Port Enable/Disable.
*/
gintsts.d32 = 0;
gintsts.b.portintr = 1;
dwc_write_reg32(&_core_if->core_global_regs->gintsts,
gintsts.d32);
retval |= 1;
}
return retval;
}

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510275 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_DRIVER_H__)
#define __DWC_OTG_DRIVER_H__
/** @file
* This file contains the interface to the Linux driver.
*/
#include "dwc_otg_cil.h"
/* Type declarations */
struct dwc_otg_pcd;
struct dwc_otg_hcd;
/**
* This structure is a wrapper that encapsulates the driver components used to
* manage a single DWC_otg controller.
*/
typedef struct dwc_otg_device
{
/** Base address returned from ioremap() */
void *base;
/** Pointer to the core interface structure. */
dwc_otg_core_if_t *core_if;
/** Register offset for Diagnostic API.*/
uint32_t reg_offset;
/** Pointer to the PCD structure. */
struct dwc_otg_pcd *pcd;
/** Pointer to the HCD structure. */
struct dwc_otg_hcd *hcd;
/** Flag to indicate whether the common IRQ handler is installed. */
uint8_t common_irq_installed;
/** Interrupt request number. */
unsigned int irq;
/** Physical address of Control and Status registers, used by
* release_mem_region().
*/
resource_size_t phys_addr;
/** Length of memory region, used by release_mem_region(). */
unsigned long base_len;
} dwc_otg_device_t;
//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg)
#endif

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef DWC_DEVICE_ONLY
#if !defined(__DWC_HCD_H__)
#define __DWC_HCD_H__
#include <linux/list.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
struct lm_device;
struct dwc_otg_device;
#include "dwc_otg_cil.h"
//#include "dwc_otg_ifx.h" // winder
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Host Contoller Driver (HCD).
*
* The Host Controller Driver (HCD) is responsible for translating requests
* from the USB Driver into the appropriate actions on the DWC_otg controller.
* It isolates the USBD from the specifics of the controller by providing an
* API to the USBD.
*/
/**
* Phases for control transfers.
*/
typedef enum dwc_otg_control_phase {
DWC_OTG_CONTROL_SETUP,
DWC_OTG_CONTROL_DATA,
DWC_OTG_CONTROL_STATUS
} dwc_otg_control_phase_e;
/** Transaction types. */
typedef enum dwc_otg_transaction_type {
DWC_OTG_TRANSACTION_NONE,
DWC_OTG_TRANSACTION_PERIODIC,
DWC_OTG_TRANSACTION_NON_PERIODIC,
DWC_OTG_TRANSACTION_ALL
} dwc_otg_transaction_type_e;
/**
* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
* interrupt, or isochronous transfer. A single QTD is created for each URB
* (of one of these types) submitted to the HCD. The transfer associated with
* a QTD may require one or multiple transactions.
*
* A QTD is linked to a Queue Head, which is entered in either the
* non-periodic or periodic schedule for execution. When a QTD is chosen for
* execution, some or all of its transactions may be executed. After
* execution, the state of the QTD is updated. The QTD may be retired if all
* its transactions are complete or if an error occurred. Otherwise, it
* remains in the schedule so more transactions can be executed later.
*/
struct dwc_otg_qh;
typedef struct dwc_otg_qtd {
/**
* Determines the PID of the next data packet for the data phase of
* control transfers. Ignored for other transfer types.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Current phase for control transfers (Setup, Data, or Status). */
dwc_otg_control_phase_e control_phase;
/** Keep track of the current split type
* for FS/LS endpoints on a HS Hub */
uint8_t complete_split;
/** How many bytes transferred during SSPLIT OUT */
uint32_t ssplit_out_xfer_count;
/**
* Holds the number of bus errors that have occurred for a transaction
* within this transfer.
*/
uint8_t error_count;
/**
* Index of the next frame descriptor for an isochronous transfer. A
* frame descriptor describes the buffer position and length of the
* data to be transferred in the next scheduled (micro)frame of an
* isochronous transfer. It also holds status for that transaction.
* The frame index starts at 0.
*/
int isoc_frame_index;
/** Position of the ISOC split on full/low speed */
uint8_t isoc_split_pos;
/** Position of the ISOC split in the buffer for the current frame */
uint16_t isoc_split_offset;
/** URB for this transfer */
struct urb *urb;
/** This list of QTDs */
struct list_head qtd_list_entry;
/* Field to track the qh pointer */
struct dwc_otg_qh *qtd_qh_ptr;
} dwc_otg_qtd_t;
/**
* A Queue Head (QH) holds the static characteristics of an endpoint and
* maintains a list of transfers (QTDs) for that endpoint. A QH structure may
* be entered in either the non-periodic or periodic schedule.
*/
typedef struct dwc_otg_qh {
/**
* Endpoint type.
* One of the following values:
* - USB_ENDPOINT_XFER_CONTROL
* - USB_ENDPOINT_XFER_ISOC
* - USB_ENDPOINT_XFER_BULK
* - USB_ENDPOINT_XFER_INT
*/
uint8_t ep_type;
uint8_t ep_is_in;
/** wMaxPacketSize Field of Endpoint Descriptor. */
uint16_t maxp;
/**
* Determines the PID of the next data packet for non-control
* transfers. Ignored for control transfers.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Ping state if 1. */
uint8_t ping_state;
/**
* List of QTDs for this QH.
*/
struct list_head qtd_list;
/** Host channel currently processing transfers for this QH. */
dwc_hc_t *channel;
/** QTD currently assigned to a host channel for this QH. */
dwc_otg_qtd_t *qtd_in_process;
/** Full/low speed endpoint on high-speed hub requires split. */
uint8_t do_split;
/** @name Periodic schedule information */
/** @{ */
/** Bandwidth in microseconds per (micro)frame. */
uint8_t usecs;
/** Interval between transfers in (micro)frames. */
uint16_t interval;
/**
* (micro)frame to initialize a periodic transfer. The transfer
* executes in the following (micro)frame.
*/
uint16_t sched_frame;
/** (micro)frame at which last start split was initialized. */
uint16_t start_split_frame;
/** @} */
uint16_t speed;
uint16_t frame_usecs[8];
/** Entry for QH in either the periodic or non-periodic schedule. */
struct list_head qh_list_entry;
} dwc_otg_qh_t;
/**
* This structure holds the state of the HCD, including the non-periodic and
* periodic schedules.
*/
typedef struct dwc_otg_hcd {
spinlock_t lock;
/** DWC OTG Core Interface Layer */
dwc_otg_core_if_t *core_if;
/** Internal DWC HCD Flags */
volatile union dwc_otg_hcd_internal_flags {
uint32_t d32;
struct {
unsigned port_connect_status_change : 1;
unsigned port_connect_status : 1;
unsigned port_reset_change : 1;
unsigned port_enable_change : 1;
unsigned port_suspend_change : 1;
unsigned port_over_current_change : 1;
unsigned reserved : 27;
} b;
} flags;
/**
* Inactive items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are not
* currently assigned to a host channel.
*/
struct list_head non_periodic_sched_inactive;
/**
* Deferred items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are not
* currently assigned to a host channel.
* When we get an NAK, the QH goes here.
*/
struct list_head non_periodic_sched_deferred;
/**
* Active items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are
* currently assigned to a host channel.
*/
struct list_head non_periodic_sched_active;
/**
* Pointer to the next Queue Head to process in the active
* non-periodic schedule.
*/
struct list_head *non_periodic_qh_ptr;
/**
* Inactive items in the periodic schedule. This is a list of QHs for
* periodic transfers that are _not_ scheduled for the next frame.
* Each QH in the list has an interval counter that determines when it
* needs to be scheduled for execution. This scheduling mechanism
* allows only a simple calculation for periodic bandwidth used (i.e.
* must assume that all periodic transfers may need to execute in the
* same frame). However, it greatly simplifies scheduling and should
* be sufficient for the vast majority of OTG hosts, which need to
* connect to a small number of peripherals at one time.
*
* Items move from this list to periodic_sched_ready when the QH
* interval counter is 0 at SOF.
*/
struct list_head periodic_sched_inactive;
/**
* List of periodic QHs that are ready for execution in the next
* frame, but have not yet been assigned to host channels.
*
* Items move from this list to periodic_sched_assigned as host
* channels become available during the current frame.
*/
struct list_head periodic_sched_ready;
/**
* List of periodic QHs to be executed in the next frame that are
* assigned to host channels.
*
* Items move from this list to periodic_sched_queued as the
* transactions for the QH are queued to the DWC_otg controller.
*/
struct list_head periodic_sched_assigned;
/**
* List of periodic QHs that have been queued for execution.
*
* Items move from this list to either periodic_sched_inactive or
* periodic_sched_ready when the channel associated with the transfer
* is released. If the interval for the QH is 1, the item moves to
* periodic_sched_ready because it must be rescheduled for the next
* frame. Otherwise, the item moves to periodic_sched_inactive.
*/
struct list_head periodic_sched_queued;
/**
* Total bandwidth claimed so far for periodic transfers. This value
* is in microseconds per (micro)frame. The assumption is that all
* periodic transfers may occur in the same (micro)frame.
*/
uint16_t periodic_usecs;
/**
* Total bandwidth claimed so far for all periodic transfers
* in a frame.
* This will include a mixture of HS and FS transfers.
* Units are microseconds per (micro)frame.
* We have a budget per frame and have to schedule
* transactions accordingly.
* Watch out for the fact that things are actually scheduled for the
* "next frame".
*/
uint16_t frame_usecs[8];
/**
* Frame number read from the core at SOF. The value ranges from 0 to
* DWC_HFNUM_MAX_FRNUM.
*/
uint16_t frame_number;
/**
* Free host channels in the controller. This is a list of
* dwc_hc_t items.
*/
struct list_head free_hc_list;
/**
* Number of available host channels.
*/
int available_host_channels;
/**
* Array of pointers to the host channel descriptors. Allows accessing
* a host channel descriptor given the host channel number. This is
* useful in interrupt handlers.
*/
dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
/**
* Buffer to use for any data received during the status phase of a
* control transfer. Normally no data is transferred during the status
* phase. This buffer is used as a bit bucket.
*/
uint8_t *status_buf;
/**
* DMA address for status_buf.
*/
dma_addr_t status_buf_dma;
#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
/**
* Structure to allow starting the HCD in a non-interrupt context
* during an OTG role change.
*/
struct work_struct start_work;
struct usb_hcd *_p;
/**
* Connection timer. An OTG host must display a message if the device
* does not connect. Started when the VBus power is turned on via
* sysfs attribute "buspower".
*/
struct timer_list conn_timer;
/* Tasket to do a reset */
struct tasklet_struct *reset_tasklet;
#ifdef DEBUG
uint32_t frrem_samples;
uint64_t frrem_accum;
uint32_t hfnum_7_samples_a;
uint64_t hfnum_7_frrem_accum_a;
uint32_t hfnum_0_samples_a;
uint64_t hfnum_0_frrem_accum_a;
uint32_t hfnum_other_samples_a;
uint64_t hfnum_other_frrem_accum_a;
uint32_t hfnum_7_samples_b;
uint64_t hfnum_7_frrem_accum_b;
uint32_t hfnum_0_samples_b;
uint64_t hfnum_0_frrem_accum_b;
uint32_t hfnum_other_samples_b;
uint64_t hfnum_other_frrem_accum_b;
#endif
} dwc_otg_hcd_t;
/** Gets the dwc_otg_hcd from a struct usb_hcd */
static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
{
return (dwc_otg_hcd_t *)(hcd->hcd_priv);
}
/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
{
return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
}
/** @name HCD Create/Destroy Functions */
/** @{ */
extern int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device);
extern void dwc_otg_hcd_remove(struct device *_dev);
/** @} */
/** @name Linux HC Driver API Functions */
/** @{ */
extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
struct urb *urb,
gfp_t mem_flags);
extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
struct urb *urb,
int status);
extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
struct usb_host_endpoint *ep);
extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
char *buf);
extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
u16 typeReq,
u16 wValue,
u16 wIndex,
char *buf,
u16 wLength);
/** @} */
/** @name Transaction Execution Functions */
/** @{ */
extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd);
extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
dwc_otg_transaction_type_e _tr_type);
extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *_urb,
int _status);
/** @} */
/** @name Interrupt Handler Functions */
/** @{ */
extern int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num);
extern int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
/** @} */
/** @name Schedule Queue Functions */
/** @{ */
/* Implemented in dwc_otg_hcd_queue.c */
extern dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb);
extern void dwc_otg_hcd_qh_init (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb);
extern void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh);
extern int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
extern void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
extern void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_csplit);
extern int dwc_otg_hcd_qh_deferr (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int delay);
/** Remove and free a QH */
static inline void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *_hcd,
dwc_otg_qh_t *_qh)
{
dwc_otg_hcd_qh_remove (_hcd, _qh);
dwc_otg_hcd_qh_free (_qh);
}
/** Allocates memory for a QH structure.
* @return Returns the memory allocate or NULL on error. */
static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc (void)
{
#ifdef _SC_BUILD_
return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_ATOMIC);
#else
return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_KERNEL);
#endif
}
extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb);
extern void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb);
extern int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
/** Allocates memory for a QTD structure.
* @return Returns the memory allocate or NULL on error. */
static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc (void)
{
#ifdef _SC_BUILD_
return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_ATOMIC);
#else
return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_KERNEL);
#endif
}
/** Frees the memory for a QTD structure. QTD should already be removed from
* list.
* @param[in] _qtd QTD to free.*/
static inline void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *_qtd)
{
kfree (_qtd);
}
/** Removes a QTD from list.
* @param[in] _qtd QTD to remove from list. */
static inline void dwc_otg_hcd_qtd_remove (dwc_otg_qtd_t *_qtd)
{
unsigned long flags;
local_irq_save (flags);
list_del (&_qtd->qtd_list_entry);
local_irq_restore (flags);
}
/** Remove and free a QTD */
static inline void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_qtd_t *_qtd)
{
dwc_otg_hcd_qtd_remove (_qtd);
dwc_otg_hcd_qtd_free (_qtd);
}
/** @} */
/** @name Internal Functions */
/** @{ */
dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb);
void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd);
void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd);
/** @} */
/** Gets the usb_host_endpoint associated with an URB. */
static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *_urb)
{
struct usb_device *dev = _urb->dev;
int ep_num = usb_pipeendpoint(_urb->pipe);
if (usb_pipein(_urb->pipe))
return dev->ep_in[ep_num];
else
return dev->ep_out[ep_num];
}
/**
* Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
* qualified with its direction (possible 32 endpoints per device).
*/
#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) \
((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
/** Gets the QH that contains the list_head */
#define dwc_list_to_qh(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qh_t,qh_list_entry))
/** Gets the QTD that contains the list_head */
#define dwc_list_to_qtd(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qtd_t,qtd_list_entry))
/** Check if QH is non-periodic */
#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
(_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
/** Packet size for any kind of endpoint descriptor */
#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
/**
* Returns true if _frame1 is less than or equal to _frame2. The comparison is
* done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
* frame number when the max frame number is reached.
*/
static inline int dwc_frame_num_le(uint16_t _frame1, uint16_t _frame2)
{
return ((_frame2 - _frame1) & DWC_HFNUM_MAX_FRNUM) <=
(DWC_HFNUM_MAX_FRNUM >> 1);
}
/**
* Returns true if _frame1 is greater than _frame2. The comparison is done
* modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
* number when the max frame number is reached.
*/
static inline int dwc_frame_num_gt(uint16_t _frame1, uint16_t _frame2)
{
return (_frame1 != _frame2) &&
(((_frame1 - _frame2) & DWC_HFNUM_MAX_FRNUM) <
(DWC_HFNUM_MAX_FRNUM >> 1));
}
/**
* Increments _frame by the amount specified by _inc. The addition is done
* modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
*/
static inline uint16_t dwc_frame_num_inc(uint16_t _frame, uint16_t _inc)
{
return (_frame + _inc) & DWC_HFNUM_MAX_FRNUM;
}
static inline uint16_t dwc_full_frame_num (uint16_t _frame)
{
return ((_frame) & DWC_HFNUM_MAX_FRNUM) >> 3;
}
static inline uint16_t dwc_micro_frame_num (uint16_t _frame)
{
return (_frame) & 0x7;
}
#ifdef DEBUG
/**
* Macro to sample the remaining PHY clocks left in the current frame. This
* may be used during debugging to determine the average time it takes to
* execute sections of code. There are two possible sample points, "a" and
* "b", so the _letter argument must be one of these values.
*
* To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
* example, "cat /sys/devices/lm0/hcd_frrem".
*/
#define dwc_sample_frrem(_hcd, _qh, _letter) \
{ \
hfnum_data_t hfnum; \
dwc_otg_qtd_t *qtd; \
qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
switch (hfnum.b.frnum & 0x7) { \
case 7: \
_hcd->hfnum_7_samples_##_letter++; \
_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
case 0: \
_hcd->hfnum_0_samples_##_letter++; \
_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
default: \
_hcd->hfnum_other_samples_##_letter++; \
_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
} \
} \
}
#else // DEBUG
#define dwc_sample_frrem(_hcd, _qh, _letter)
#endif // DEBUG
#endif // __DWC_HCD_H__
#endif /* DWC_DEVICE_ONLY */

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef DWC_DEVICE_ONLY
/**
* @file
*
* This file contains the functions to manage Queue Heads and Queue
* Transfer Descriptors.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include "dwc_otg_driver.h"
#include "dwc_otg_hcd.h"
#include "dwc_otg_regs.h"
/**
* This function allocates and initializes a QH.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param[in] _urb Holds the information about the device/endpoint that we need
* to initialize the QH.
*
* @return Returns pointer to the newly allocated QH, or NULL on error. */
dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
{
dwc_otg_qh_t *qh;
/* Allocate memory */
/** @todo add memflags argument */
qh = dwc_otg_hcd_qh_alloc ();
if (qh == NULL) {
return NULL;
}
dwc_otg_hcd_qh_init (_hcd, qh, _urb);
return qh;
}
/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
* removed from a list. QTD list should already be empty if called from URB
* Dequeue.
*
* @param[in] _qh The QH to free.
*/
void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
{
dwc_otg_qtd_t *qtd;
struct list_head *pos;
unsigned long flags;
/* Free each QTD in the QTD list */
local_irq_save (flags);
for (pos = _qh->qtd_list.next;
pos != &_qh->qtd_list;
pos = _qh->qtd_list.next)
{
list_del (pos);
qtd = dwc_list_to_qtd (pos);
dwc_otg_hcd_qtd_free (qtd);
}
local_irq_restore (flags);
kfree (_qh);
return;
}
/** Initializes a QH structure.
*
* @param[in] _hcd The HCD state structure for the DWC OTG controller.
* @param[in] _qh The QH to init.
* @param[in] _urb Holds the information about the device/endpoint that we need
* to initialize the QH. */
#define SCHEDULE_SLOP 10
void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
{
memset (_qh, 0, sizeof (dwc_otg_qh_t));
/* Initialize QH */
switch (usb_pipetype(_urb->pipe)) {
case PIPE_CONTROL:
_qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
break;
case PIPE_BULK:
_qh->ep_type = USB_ENDPOINT_XFER_BULK;
break;
case PIPE_ISOCHRONOUS:
_qh->ep_type = USB_ENDPOINT_XFER_ISOC;
break;
case PIPE_INTERRUPT:
_qh->ep_type = USB_ENDPOINT_XFER_INT;
break;
}
_qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
_qh->data_toggle = DWC_OTG_HC_PID_DATA0;
_qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
INIT_LIST_HEAD(&_qh->qtd_list);
INIT_LIST_HEAD(&_qh->qh_list_entry);
_qh->channel = NULL;
/* FS/LS Enpoint on HS Hub
* NOT virtual root hub */
_qh->do_split = 0;
_qh->speed = _urb->dev->speed;
if (((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)) &&
(_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) {
DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
_urb->dev->ttport);
_qh->do_split = 1;
}
if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
_qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
/* Compute scheduling parameters once and save them. */
hprt0_data_t hprt;
/** @todo Account for split transfers in the bus time. */
int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
_qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed,
usb_pipein(_urb->pipe),
(_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount));
/* Start in a slightly future (micro)frame. */
_qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP);
_qh->interval = _urb->interval;
#if 0
/* Increase interrupt polling rate for debugging. */
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
_qh->interval = 8;
}
#endif
hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)))
{
_qh->interval *= 8;
_qh->sched_frame |= 0x7;
_qh->start_split_frame = _qh->sched_frame;
}
}
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
_urb->dev->devnum);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
usb_pipeendpoint(_urb->pipe),
usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
({ char *speed; switch (_urb->dev->speed) {
case USB_SPEED_LOW: speed = "low"; break;
case USB_SPEED_FULL: speed = "full"; break;
case USB_SPEED_HIGH: speed = "high"; break;
default: speed = "?"; break;
}; speed;}));
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
({ char *type; switch (_qh->ep_type) {
case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
default: type = "?"; break;
}; type;}));
#ifdef DEBUG
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
_qh->usecs);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
_qh->interval);
}
#endif
return;
}
/**
* Microframe scheduler
* track the total use in hcd->frame_usecs
* keep each qh use in qh->frame_usecs
* when surrendering the qh then donate the time back
*/
const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
/*
* called from dwc_otg_hcd.c:dwc_otg_hcd_init
*/
int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
{
int i;
for (i=0; i<8; i++) {
_hcd->frame_usecs[i] = max_uframe_usecs[i];
}
return 0;
}
static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int i;
unsigned short utime;
int t_left;
int ret;
int done;
ret = -1;
utime = _qh->usecs;
t_left = utime;
i = 0;
done = 0;
while (done == 0) {
/* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
if (utime <= _hcd->frame_usecs[i]) {
_hcd->frame_usecs[i] -= utime;
_qh->frame_usecs[i] += utime;
t_left -= utime;
ret = i;
done = 1;
return ret;
} else {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
}
}
return ret;
}
/*
* use this for FS apps that can span multiple uframes
*/
static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int i;
int j;
unsigned short utime;
int t_left;
int ret;
int done;
unsigned short xtime;
ret = -1;
utime = _qh->usecs;
t_left = utime;
i = 0;
done = 0;
loop:
while (done == 0) {
if(_hcd->frame_usecs[i] <= 0) {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
goto loop;
}
/*
* we need n consequtive slots
* so use j as a start slot j plus j+1 must be enough time (for now)
*/
xtime= _hcd->frame_usecs[i];
for (j = i+1 ; j < 8 ; j++ ) {
/*
* if we add this frame remaining time to xtime we may
* be OK, if not we need to test j for a complete frame
*/
if ((xtime+_hcd->frame_usecs[j]) < utime) {
if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
j = 8;
ret = -1;
continue;
}
}
if (xtime >= utime) {
ret = i;
j = 8; /* stop loop with a good value ret */
continue;
}
/* add the frame time to x time */
xtime += _hcd->frame_usecs[j];
/* we must have a fully available next frame or break */
if ((xtime < utime)
&& (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
ret = -1;
j = 8; /* stop loop with a bad value ret */
continue;
}
}
if (ret >= 0) {
t_left = utime;
for (j = i; (t_left>0) && (j < 8); j++ ) {
t_left -= _hcd->frame_usecs[j];
if ( t_left <= 0 ) {
_qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
_hcd->frame_usecs[j]= -t_left;
ret = i;
done = 1;
} else {
_qh->frame_usecs[j] += _hcd->frame_usecs[j];
_hcd->frame_usecs[j] = 0;
}
}
} else {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
}
}
return ret;
}
static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int ret;
ret = -1;
if (_qh->speed == USB_SPEED_HIGH) {
/* if this is a hs transaction we need a full frame */
ret = find_single_uframe(_hcd, _qh);
} else {
/* if this is a fs transaction we may need a sequence of frames */
ret = find_multi_uframe(_hcd, _qh);
}
return ret;
}
/**
* Checks that the max transfer size allowed in a host channel is large enough
* to handle the maximum data transfer in a single (micro)frame for a periodic
* transfer.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for a periodic endpoint.
*
* @return 0 if successful, negative error code otherwise.
*/
static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int status;
uint32_t max_xfer_size;
uint32_t max_channel_xfer_size;
status = 0;
max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
if (max_xfer_size > max_channel_xfer_size) {
DWC_NOTICE("%s: Periodic xfer length %d > "
"max xfer length for channel %d\n",
__func__, max_xfer_size, max_channel_xfer_size);
status = -ENOSPC;
}
return status;
}
/**
* Schedules an interrupt or isochronous transfer in the periodic schedule.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for the periodic transfer. The QH should already contain the
* scheduling information.
*
* @return 0 if successful, negative error code otherwise.
*/
static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int status = 0;
int frame;
status = find_uframe(_hcd, _qh);
frame = -1;
if (status == 0) {
frame = 7;
} else {
if (status > 0 )
frame = status-1;
}
/* Set the new frame up */
if (frame > -1) {
_qh->sched_frame &= ~0x7;
_qh->sched_frame |= (frame & 7);
}
if (status != -1 )
status = 0;
if (status) {
DWC_NOTICE("%s: Insufficient periodic bandwidth for "
"periodic transfer.\n", __func__);
return status;
}
status = check_max_xfer_size(_hcd, _qh);
if (status) {
DWC_NOTICE("%s: Channel max transfer size too small "
"for periodic transfer.\n", __func__);
return status;
}
/* Always start in the inactive schedule. */
list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
/* Update claimed usecs per (micro)frame. */
_hcd->periodic_usecs += _qh->usecs;
/* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
} else {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
}
return status;
}
/**
* This function adds a QH to either the non periodic or periodic schedule if
* it is not already in the schedule. If the QH is already in the schedule, no
* action is taken.
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
unsigned long flags;
int status = 0;
local_irq_save(flags);
if (!list_empty(&_qh->qh_list_entry)) {
/* QH already in a schedule. */
goto done;
}
/* Add the new QH to the appropriate schedule */
if (dwc_qh_is_non_per(_qh)) {
/* Always start in the inactive schedule. */
list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
} else {
status = schedule_periodic(_hcd, _qh);
}
done:
local_irq_restore(flags);
return status;
}
/**
* This function adds a QH to the non periodic deferred schedule.
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
unsigned long flags;
local_irq_save(flags);
if (!list_empty(&_qh->qh_list_entry)) {
/* QH already in a schedule. */
goto done;
}
/* Add the new QH to the non periodic deferred schedule */
if (dwc_qh_is_non_per(_qh)) {
list_add_tail(&_qh->qh_list_entry,
&_hcd->non_periodic_sched_deferred);
}
done:
local_irq_restore(flags);
return 0;
}
/**
* Removes an interrupt or isochronous transfer from the periodic schedule.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for the periodic transfer.
*/
static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int i;
list_del_init(&_qh->qh_list_entry);
/* Update claimed usecs per (micro)frame. */
_hcd->periodic_usecs -= _qh->usecs;
for (i = 0; i < 8; i++) {
_hcd->frame_usecs[i] += _qh->frame_usecs[i];
_qh->frame_usecs[i] = 0;
}
/* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
} else {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
}
}
/**
* Removes a QH from either the non-periodic or periodic schedule. Memory is
* not freed.
*
* @param[in] _hcd The HCD state structure.
* @param[in] _qh QH to remove from schedule. */
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_qh->qh_list_entry)) {
/* QH is not in a schedule. */
goto done;
}
if (dwc_qh_is_non_per(_qh)) {
if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
_hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
}
list_del_init(&_qh->qh_list_entry);
} else {
deschedule_periodic(_hcd, _qh);
}
done:
local_irq_restore(flags);
}
/**
* Defers a QH. For non-periodic QHs, removes the QH from the active
* non-periodic schedule. The QH is added to the deferred non-periodic
* schedule if any QTDs are still attached to the QH.
*/
int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay)
{
int deact = 1;
unsigned long flags;
local_irq_save(flags);
if (dwc_qh_is_non_per(_qh)) {
_qh->sched_frame =
dwc_frame_num_inc(_hcd->frame_number,
delay);
_qh->channel = NULL;
_qh->qtd_in_process = NULL;
deact = 0;
dwc_otg_hcd_qh_remove(_hcd, _qh);
if (!list_empty(&_qh->qtd_list)) {
/* Add back to deferred non-periodic schedule. */
dwc_otg_hcd_qh_add_deferred(_hcd, _qh);
}
}
local_irq_restore(flags);
return deact;
}
/**
* Deactivates a QH. For non-periodic QHs, removes the QH from the active
* non-periodic schedule. The QH is added to the inactive non-periodic
* schedule if any QTDs are still attached to the QH.
*
* For periodic QHs, the QH is removed from the periodic queued schedule. If
* there are any QTDs still attached to the QH, the QH is added to either the
* periodic inactive schedule or the periodic ready schedule and its next
* scheduled frame is calculated. The QH is placed in the ready schedule if
* the scheduled frame has been reached already. Otherwise it's placed in the
* inactive schedule. If there are no QTDs attached to the QH, the QH is
* completely removed from the periodic schedule.
*/
void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
{
unsigned long flags;
local_irq_save(flags);
if (dwc_qh_is_non_per(_qh)) {
dwc_otg_hcd_qh_remove(_hcd, _qh);
if (!list_empty(&_qh->qtd_list)) {
/* Add back to inactive non-periodic schedule. */
dwc_otg_hcd_qh_add(_hcd, _qh);
}
} else {
uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
if (_qh->do_split) {
/* Schedule the next continuing periodic split transfer */
if (sched_next_periodic_split) {
_qh->sched_frame = frame_number;
if (dwc_frame_num_le(frame_number,
dwc_frame_num_inc(_qh->start_split_frame, 1))) {
/*
* Allow one frame to elapse after start
* split microframe before scheduling
* complete split, but DONT if we are
* doing the next start split in the
* same frame for an ISOC out.
*/
if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
_qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
}
}
} else {
_qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
_qh->interval);
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
_qh->sched_frame = frame_number;
}
_qh->sched_frame |= 0x7;
_qh->start_split_frame = _qh->sched_frame;
}
} else {
_qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
_qh->sched_frame = frame_number;
}
}
if (list_empty(&_qh->qtd_list)) {
dwc_otg_hcd_qh_remove(_hcd, _qh);
} else {
/*
* Remove from periodic_sched_queued and move to
* appropriate queue.
*/
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
list_move(&_qh->qh_list_entry,
&_hcd->periodic_sched_ready);
} else {
list_move(&_qh->qh_list_entry,
&_hcd->periodic_sched_inactive);
}
}
}
local_irq_restore(flags);
}
/**
* This function allocates and initializes a QTD.
*
* @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
* pointing to each other so each pair should have a unique correlation.
*
* @return Returns pointer to the newly allocated QTD, or NULL on error. */
dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
{
dwc_otg_qtd_t *qtd;
qtd = dwc_otg_hcd_qtd_alloc ();
if (qtd == NULL) {
return NULL;
}
dwc_otg_hcd_qtd_init (qtd, _urb);
return qtd;
}
/**
* Initializes a QTD structure.
*
* @param[in] _qtd The QTD to initialize.
* @param[in] _urb The URB to use for initialization. */
void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
{
memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
_qtd->urb = _urb;
if (usb_pipecontrol(_urb->pipe)) {
/*
* The only time the QTD data toggle is used is on the data
* phase of control transfers. This phase always starts with
* DATA1.
*/
_qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
_qtd->control_phase = DWC_OTG_CONTROL_SETUP;
}
/* start split */
_qtd->complete_split = 0;
_qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
_qtd->isoc_split_offset = 0;
/* Store the qtd ptr in the urb to reference what QTD. */
_urb->hcpriv = _qtd;
return;
}
/**
* This function adds a QTD to the QTD-list of a QH. It will find the correct
* QH to place the QTD into. If it does not find a QH, then it will create a
* new QH. If the QH to which the QTD is added is not currently scheduled, it
* is placed into the proper schedule based on its EP type.
*
* @param[in] _qtd The QTD to add
* @param[in] _dwc_otg_hcd The DWC HCD structure
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd)
{
struct usb_host_endpoint *ep;
dwc_otg_qh_t *qh;
unsigned long flags;
int retval = 0;
struct urb *urb = _qtd->urb;
local_irq_save(flags);
/*
* Get the QH which holds the QTD-list to insert to. Create QH if it
* doesn't exist.
*/
ep = dwc_urb_to_endpoint(urb);
qh = (dwc_otg_qh_t *)ep->hcpriv;
if (qh == NULL) {
qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
if (qh == NULL) {
retval = -1;
goto done;
}
ep->hcpriv = qh;
}
_qtd->qtd_qh_ptr = qh;
retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
if (retval == 0) {
list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
}
done:
local_irq_restore(flags);
return retval;
}
#endif /* DWC_DEVICE_ONLY */

103
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/******************************************************************************
**
** FILE NAME : dwc_otg_ifx.c
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 12 Auguest 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Platform specific initialization.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 Auguest 2007 Sung Winder Initiate Version
*******************************************************************************/
#include "dwc_otg_ifx.h"
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/gpio.h>
#include <asm/io.h>
//#include <asm/mach-ifxmips/ifxmips.h>
#include <lantiq_soc.h>
#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
#define writel ltq_w32
#define readl ltq_r32
void dwc_otg_power_on (void)
{
// clear power
writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
// set clock gating
if (ltq_is_ase())
writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR);
else
writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
// set power
writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);
writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR);
#if 1//defined (DWC_HOST_ONLY)
// make the hardware be a host controller (default)
//clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_HDSEL_BIT), DANUBE_RCU_UBSCFG);
//#elif defined (DWC_DEVICE_ONLY)
/* set the controller to the device mode */
// set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
#else
#error "For Danube/Twinpass, it should be HOST or Device Only."
#endif
// set the HC's byte-order to big-endian
//set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) | (1<<DANUBE_USBCFG_HOST_END_BIT), DANUBE_RCU_UBSCFG);
//clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_SLV_END_BIT), DANUBE_RCU_UBSCFG);
//writel(0x400, DANUBE_RCU_UBSCFG);
// PHY configurations.
writel (0x14014, (volatile unsigned long *)0xbe10103c);
}
int ifx_usb_hc_init(unsigned long base_addr, int irq)
{
return 0;
}
void ifx_usb_hc_remove(void)
{
}

85
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/******************************************************************************
**
** FILE NAME : dwc_otg_ifx.h
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 12 April 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Platform specific initialization.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 April 2007 Sung Winder Initiate Version
*******************************************************************************/
#if !defined(__DWC_OTG_IFX_H__)
#define __DWC_OTG_IFX_H__
#include <linux/irq.h>
#include <irq.h>
// 20070316, winder added.
#ifndef SZ_256K
#define SZ_256K 0x00040000
#endif
extern void dwc_otg_power_on (void);
/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */
// #include <asm/danube/danube.h>
// #include <asm/ifx/irq.h>
/* winder, I used the Danube parameter as default. *
* We could change this through module param. */
#define IFX_USB_IOMEM_BASE 0x1e101000
#define IFX_USB_IOMEM_SIZE SZ_256K
#define IFX_USB_IRQ LTQ_USB_INT
/**
* This function is called to set correct clock gating and power.
* For Twinpass/Danube board.
*/
#ifndef DANUBE_RCU_BASE_ADDR
#define DANUBE_RCU_BASE_ADDR (0xBF203000)
#endif
#ifndef DANUBE_CGU
#define DANUBE_CGU (0xBF103000)
#endif
#ifndef DANUBE_CGU_IFCCR
/***CGU Interface Clock Control Register***/
#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
#endif
#ifndef DANUBE_PMU
#define DANUBE_PMU (KSEG1+0x1F102000)
#endif
#ifndef DANUBE_PMU_PWDCR
/* PMU Power down Control Register */
#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C))
#endif
#define DANUBE_RCU_UBSCFG ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18))
#define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device
#define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end
#define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end
extern void ltq_mask_and_ack_irq(struct irq_data *d);
static void inline mask_and_ack_ifx_irq(int x)
{
struct irq_data d;
d.irq = x;
ltq_mask_and_ack_irq(&d);
}
#endif //__DWC_OTG_IFX_H__

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/platform/dwc_otg_plat.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510301 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_PLAT_H__)
#define __DWC_OTG_PLAT_H__
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <asm/io.h>
/**
* @file
*
* This file contains the Platform Specific constants, interfaces
* (functions and macros) for Linux.
*
*/
/*#if !defined(__LINUX__)
#error "The contents of this file is Linux specific!!!"
#endif
*/
#include <lantiq_soc.h>
#define writel ltq_w32
#define readl ltq_r32
/**
* Reads the content of a register.
*
* @param _reg address of register to read.
* @return contents of the register.
*
* Usage:<br>
* <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
*/
static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg)
{
return readl(_reg);
};
/**
* Writes a register with a 32 bit value.
*
* @param _reg address of register to read.
* @param _value to write to _reg.
*
* Usage:<br>
* <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
*/
static __inline__ void dwc_write_reg32( volatile uint32_t *_reg, const uint32_t _value)
{
writel( _value, _reg );
};
/**
* This function modifies bit values in a register. Using the
* algorithm: (reg_contents & ~clear_mask) | set_mask.
*
* @param _reg address of register to read.
* @param _clear_mask bit mask to be cleared.
* @param _set_mask bit mask to be set.
*
* Usage:<br>
* <code> // Clear the SOF Interrupt Mask bit and <br>
* // set the OTG Interrupt mask bit, leaving all others as they were.
* dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
*/
static __inline__
void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
{
writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg );
};
/**
* Wrapper for the OS micro-second delay function.
* @param[in] _usecs Microseconds of delay
*/
static __inline__ void UDELAY( const uint32_t _usecs )
{
udelay( _usecs );
}
/**
* Wrapper for the OS milli-second delay function.
* @param[in] _msecs milliseconds of delay
*/
static __inline__ void MDELAY( const uint32_t _msecs )
{
mdelay( _msecs );
}
/**
* Wrapper for the Linux spin_lock. On the ARM (Integrator)
* spin_lock() is a nop.
*
* @param _lock Pointer to the spinlock.
*/
static __inline__ void SPIN_LOCK( spinlock_t *_lock )
{
spin_lock(_lock);
}
/**
* Wrapper for the Linux spin_unlock. On the ARM (Integrator)
* spin_lock() is a nop.
*
* @param _lock Pointer to the spinlock.
*/
static __inline__ void SPIN_UNLOCK( spinlock_t *_lock )
{
spin_unlock(_lock);
}
/**
* Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM
* (Integrator) spin_lock() is a nop.
*
* @param _l Pointer to the spinlock.
* @param _f unsigned long for irq flags storage.
*/
#define SPIN_LOCK_IRQSAVE( _l, _f ) { \
spin_lock_irqsave(_l,_f); \
}
/**
* Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM
* (Integrator) spin_lock() is a nop.
*
* @param _l Pointer to the spinlock.
* @param _f unsigned long for irq flags storage.
*/
#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) {\
spin_unlock_irqrestore(_l,_f); \
}
/*
* Debugging support vanishes in non-debug builds.
*/
/**
* The Debug Level bit-mask variable.
*/
extern uint32_t g_dbg_lvl;
/**
* Set the Debug Level variable.
*/
static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new )
{
uint32_t old = g_dbg_lvl;
g_dbg_lvl = _new;
return old;
}
/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
#define DBG_CIL (0x2)
/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
* messages */
#define DBG_CILV (0x20)
/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
* messages */
#define DBG_PCD (0x4)
/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
* messages */
#define DBG_PCDV (0x40)
/** When debug level has the DBG_HCD bit set, display Host debug messages */
#define DBG_HCD (0x8)
/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
* messages */
#define DBG_HCDV (0x80)
/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
* mode. */
#define DBG_HCD_URB (0x800)
/** When debug level has any bit set, display debug messages */
#define DBG_ANY (0xFF)
/** All debug messages off */
#define DBG_OFF 0
/** Prefix string for DWC_DEBUG print macros. */
#define USB_DWC "DWC_otg: "
/**
* Print a debug message when the Global debug level variable contains
* the bit defined in <code>lvl</code>.
*
* @param[in] lvl - Debug level, use one of the DBG_ constants above.
* @param[in] x - like printf
*
* Example:<p>
* <code>
* DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
* </code>
* <br>
* results in:<br>
* <code>
* usb-DWC_otg: dwc_otg_cil_init(ca867000)
* </code>
*/
#ifdef DEBUG
# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
#else
# define DWC_DEBUGPL(lvl, x...) do{}while(0)
# define DWC_DEBUGP(x...)
# define CHK_DEBUG_LEVEL(level) (0)
#endif /*DEBUG*/
/**
* Print an Error message.
*/
#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
/**
* Print a Warning message.
*/
#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
/**
* Print a notice (normal but significant message).
*/
#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
/**
* Basic message printing.
*/
#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
#endif

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58
target/linux/lantiq/files/drivers/usb/ifxhcd/Kconfig Normal file
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config USB_HOST_IFX
tristate "Infineon USB Host Controller Driver"
depends on USB
default n
help
Infineon USB Host Controller
config USB_HOST_IFX_B
bool "USB host mode on core 1 and 2"
depends on USB_HOST_IFX
help
Both cores run as host
#config USB_HOST_IFX_1
#config USB_HOST_IFX_2
#config IFX_DANUBE
#config IFX_AMAZON_SE
config IFX_AR9
depends on USB_HOST_IFX
bool "AR9"
config IFX_VR9
depends on USB_HOST_IFX
bool "VR9"
#config USB_HOST_IFX_FORCE_USB11
# bool "Forced USB1.1"
# depends on USB_HOST_IFX
# default n
# help
# force to be USB 1.1
#config USB_HOST_IFX_WITH_HS_ELECT_TST
# bool "With HS_Electrical Test"
# depends on USB_HOST_IFX
# default n
# help
# With USBIF HSET routines
#config USB_HOST_IFX_WITH_ISO
# bool "With ISO transfer"
# depends on USB_HOST_IFX
# default n
# help
# With USBIF ISO transfer
config USB_HOST_IFX_UNALIGNED_ADJ
bool "Adjust"
depends on USB_HOST_IFX
help
USB_HOST_IFX_UNALIGNED_ADJ
#config USB_HOST_IFX_UNALIGNED_CHK
#config USB_HOST_IFX_UNALIGNED_NONE

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target/linux/lantiq/files/drivers/usb/ifxhcd/Makefile Normal file
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#
# Makefile for USB Core files and filesystem
#
ifxusb_host-objs := ifxusb_driver.o
ifxusb_host-objs += ifxusb_ctl.o
ifxusb_host-objs += ifxusb_cif.o
ifxusb_host-objs += ifxusb_cif_h.o
ifxusb_host-objs += ifxhcd.o
ifxusb_host-objs += ifxhcd_es.o
ifxusb_host-objs += ifxhcd_intr.o
ifxusb_host-objs += ifxhcd_queue.o
ifeq ($(CONFIG_IFX_TWINPASS),y)
EXTRA_CFLAGS += -D__IS_TWINPASS__
endif
ifeq ($(CONFIG_IFX_DANUBE),y)
EXTRA_CFLAGS += -D__IS_DANUBE__
endif
ifeq ($(CONFIG_IFX_AMAZON_SE),y)
EXTRA_CFLAGS += -D__IS_AMAZON_SE__
endif
ifeq ($(CONFIG_IFX_AR9),y)
EXTRA_CFLAGS += -D__IS_AR9__
endif
ifeq ($(CONFIG_IFX_AMAZON_S),y)
EXTRA_CFLAGS += -D__IS_AR9__
endif
ifeq ($(CONFIG_IFX_VR9),y)
EXTRA_CFLAGS += -D__IS_VR9__
endif
ifeq ($(CONFIG_USB_HOST_IFX),y)
EXTRA_CFLAGS += -Dlinux -D__LINUX__
EXTRA_CFLAGS += -D__IS_HOST__
EXTRA_CFLAGS += -D__KERNEL__
endif
ifeq ($(CONFIG_USB_HOST_IFX),m)
EXTRA_CFLAGS += -Dlinux -D__LINUX__
EXTRA_CFLAGS += -D__IS_HOST__
EXTRA_CFLAGS += -D__KERNEL__
endif
ifeq ($(CONFIG_USB_DEBUG),y)
EXTRA_CFLAGS += -D__DEBUG__
EXTRA_CFLAGS += -D__ENABLE_DUMP__
endif
ifeq ($(CONFIG_USB_HOST_IFX_B),y)
EXTRA_CFLAGS += -D__IS_DUAL__
endif
ifeq ($(CONFIG_USB_HOST_IFX_1),y)
EXTRA_CFLAGS += -D__IS_FIRST__
endif
ifeq ($(CONFIG_USB_HOST_IFX_2),y)
EXTRA_CFLAGS += -D__IS_SECOND__
endif
ifeq ($(CONFIG_USB_HOST_IFX_FORCE_USB11),y)
EXTRA_CFLAGS += -D__FORCE_USB11__
endif
ifeq ($(CONFIG_USB_HOST_IFX_WITH_HS_ELECT_TST),y)
EXTRA_CFLAGS += -D__WITH_HS_ELECT_TST__
endif
ifeq ($(CONFIG_USB_HOST_IFX_WITH_ISO),y)
EXTRA_CFLAGS += -D__EN_ISOC__
endif
ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_ADJ),y)
EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_ADJ__
endif
ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_CHK),y)
EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_CHK__
endif
# EXTRA_CFLAGS += -D__DYN_SOF_INTR__
EXTRA_CFLAGS += -D__UEIP__
# EXTRA_CFLAGS += -D__EN_ISOC__
# EXTRA_CFLAGS += -D__EN_ISOC_SPLIT__
## 20110628 AVM/WK New flag for less SOF IRQs
EXTRA_CFLAGS += -D__USE_TIMER_4_SOF__
obj-$(CONFIG_USB_HOST_IFX) += ifxusb_host.o

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+----------------------------------------------------------------------+
| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.18-r240-non_musb_ar9_vr9-SOF_Timer_Fixed
| Erzeugt mit SVN-Tagger Version 3.74.
+----------------------------------------------------------------------+
FIX - Korrektur bei der SOF-Timer/IRQ Steuerung. (Bug in Tag 5.17)
FIX - Fehlerbehandlung an mehreren Stellen korrigiert bzw. eingebaut.
+----------------------------------------------------------------------+
| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.17-r237-non_musb_ar9_vr9-2_6_32_41_Kompatibel
| Erzeugt mit SVN-Tagger Version 3.73.
+----------------------------------------------------------------------+
FIX - Kompatiblität zum Update auf Kernel 2.6.32-41. Weiterhin für 28er geeignet.
ENH - Reduktion der Interrruptlast durch Nutzung eines hrtimers anstatt SOF-IRQ.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.16-r208-non_musb_ar9_vr9-20110421_Zero_Paket_Optimiert
| Erzeugt mit SVN-Tagger Version 3.66.
+----------------------------------------------------------------------+
FIX - VR9 / AR9 - Zero Packet. Optimierung korrigiert.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.15-r205-non_musb_ar9_vr9-20110421_Zero_Paket_WA_funktioniert
| Erzeugt mit SVN-Tagger Version 3.66.
+----------------------------------------------------------------------+
FIX - VR9 / AR9 - "Zero Packet" funktioniert nun wirklich. Letzter Tag hatte einen Bug.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.14-r202-non_musb_ar9_vr9-20110420_Zero_Paket_WA
| Erzeugt mit SVN-Tagger Version 3.66.
+----------------------------------------------------------------------+
FIX - VR9 / AR9 - Zero Packet Workaround: ZLP wird nun geschickt wenn URB_ZERO_PACKET aktiv ist.
Wird von LTE Altair Firmware benoetig.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.13-r199-non_musb_ar9_vr9-20110310_Init_Fix
| Erzeugt mit SVN-Tagger Version 3.64.
+----------------------------------------------------------------------+
FIX - VR9 / AR9 - Timing der Initialisierungsphase angepasst zum Kernel 2.6.28 mit UGW-4.3.1.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.12-r184-non_musb_ar9_vr9-20110118_Full_Speed_Fix
| Erzeugt mit SVN-Tagger Version 3.58.
+----------------------------------------------------------------------+
AR9/VR9 (3370,6840,7320):
Makefile - FIX - (Workaround) Debug Modus hilft gegen Enumerationsfehler bei Full Speed Drucker.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.11-r175-non_musb_ar9_vr9-20101220_VR9_2_Ports_DMA_Fix
| Erzeugt mit SVN-Tagger Version 3.58.
+----------------------------------------------------------------------+
FIX - VR9 - Workaround DMA Burst Size. Wenn beiden USB Ports benutzt werden, geht der USB Host nicht mehr.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.10-r169-non_musb_ar9_vr9-Fix_Spontan_Reboot
| Erzeugt mit SVN-Tagger Version 3.58.
+----------------------------------------------------------------------+
FIX - Endlosschleife führte zu einem spontanen Reboot.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.9-r166-non_musb_ar9_vr9-20101112_deferred_completion
| Erzeugt mit SVN-Tagger Version 3.58.
+----------------------------------------------------------------------+
ENH - Deferred URB Completion Mechanismus eingebaut. Nun ca. 10% schneller bei usb-storage.
FIX - PING Flow Control gefixt.
FIX - Channel Halt wird nun immer angerufen. (Split Transaction wurde nicht erfolgreich gestoppt).
FIX - Spinlock Benutzung verbessert. Mehr Stabilitaet.
CHG - Ubersetztungsoption __DEBUG__ ist nun abhaengig von CONFIG_USB_DEBUG
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.8-r149-non_musb_ar9_vr9-20100827_LTE_Interrupt_EP_Fix
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
AR9/VR9 - FIX - Interrupt Packets gingen verloren, wegen falschem Timing beim OddFrame Bit.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.7-r142-non_musb_ar9_vr9-20100728_Unaligned_Buf_Fix
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
FIX - "Unaligned Data" Flag wieder nach Transfer geloescht.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.6-r133-non_musb_ar9_vr9-20100714_Toggle_Datenverlust_Fix
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
TL5508 - Einige UMTS Modems funktionierten nicht korrekt an der 7320 (AR9).
FIX - USB Data Toggle des usbcore benutzen. Datenverlust nach EP-Halt.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.5-r130-non_musb_ar9_vr9-20100712_USB_Ports_abschaltbar
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
Power - Fix - Beide USB Port abschaltbar bei rmmod.
rmmod - FIX - URB_Dequeue funktionierte beim Entladen des Treibers nicht (mehrere Ursachen).
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.4-r126-non_musb_ar9_vr9-20100701_Lost_Interrupt_Workaround
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
FIX - Workaround wegen verpasstem Interrupt, bei Full-Speed Interrupt EP.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.3-r123-non_musb_ar9_vr9-20100630_UMTS_Fixes
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
FIX - Full-Speed Interrupt Endpoint hinter Hi-Speed Hub funktioniert nun (UMTS Modems)
FIX - usb_hcd_link_urb_from_ep API von USBCore muss benutzt werden.
FIX - Interrupt URBs nicht bei NAK completen.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.2-r114-non_musb_ar9_vr9-20100520_StickAndSurf_funktioniert
| Erzeugt mit SVN-Tagger Version 3.56.
+----------------------------------------------------------------------+
- Merge mit neuen LANTIQ Sourcen "3.0alpha B100312"
- Fix - Spin_lock eingebaut, Stick&Surf funktioniert nun
- DEP - CONFIG_USB_HOST_IFX_WITH_ISO wird nicht unterstuetzt: In der Kernel Config deaktivieren.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.1-r107-non_musb_ar9_vr9-20100505_IFXUSB_Host_mit_Energiemonitor
| Erzeugt mit SVN-Tagger Version 3.56.
+----------------------------------------------------------------------+
USB Host Treiber für AR9 und VR9
--------------------------------
FIX - Toggle Error nach STALL - Einfacher Workaround - Nun werden Massenspeicherpartitionen erkannt!
AVM_POWERMETER - USB Energiemonitor Support.
Bekanntes Problem: Stick and Surf funktioniert nur sporadisch, weil CONTROL_IRQ manchmal ausbleibt.

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/*****************************************************************************
** FILE NAME : ifxhcd.h
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : This file contains the structures, constants, and interfaces for
** the Host Contoller Driver (HCD).
**
** The Host Controller Driver (HCD) is responsible for translating requests
** from the USB Driver into the appropriate actions on the IFXUSB controller.
** It isolates the USBD from the specifics of the controller by providing an
** API to the USBD.
** FUNCTIONS :
** COMPILER : gcc
** REFERENCE : Synopsys DWC-OTG Driver 2.7
** COPYRIGHT :
** Version Control Section **
** $Author$
** $Date$
** $Revisions$
** $Log$ Revision history
*****************************************************************************/
/*!
\defgroup IFXUSB_HCD HCD Interface
\ingroup IFXUSB_DRIVER_V3
\brief The Host Controller Driver (HCD) is responsible for translating requests
from the USB Driver into the appropriate actions on the IFXUSB controller.
It isolates the USBD from the specifics of the controller by providing an
API to the USBD.
*/
/*!
\file ifxhcd.h
\ingroup IFXUSB_DRIVER_V3
\brief This file contains the structures, constants, and interfaces for
the Host Contoller Driver (HCD).
*/
#if !defined(__IFXHCD_H__)
#define __IFXHCD_H__
#include <linux/list.h>
#include <linux/usb.h>
#ifdef __USE_TIMER_4_SOF__
#include <linux/hrtimer.h>
#endif
#include <linux/usb/hcd.h>
#include "ifxusb_cif.h"
#include "ifxusb_plat.h"
/*!
\addtogroup IFXUSB_HCD
*/
/*@{*/
/* Phases for control transfers.*/
typedef enum ifxhcd_control_phase {
IFXHCD_CONTROL_SETUP,
IFXHCD_CONTROL_DATA,
IFXHCD_CONTROL_STATUS
} ifxhcd_control_phase_e;
/* Reasons for halting a host channel. */
typedef enum ifxhcd_halt_status
{
HC_XFER_NO_HALT_STATUS, // Initial
HC_XFER_COMPLETE, // Xact complete without error, upward
HC_XFER_URB_COMPLETE, // Xfer complete without error, short upward
HC_XFER_STALL, // HC stopped abnormally, upward/downward
HC_XFER_XACT_ERR, // HC stopped abnormally, upward
HC_XFER_FRAME_OVERRUN, // HC stopped abnormally, upward
HC_XFER_BABBLE_ERR, // HC stopped abnormally, upward
HC_XFER_AHB_ERR, // HC stopped abnormally, upward
HC_XFER_DATA_TOGGLE_ERR,
HC_XFER_URB_DEQUEUE, // HC stopper manually, downward
HC_XFER_NAK // HC stopped by nak monitor, downward
} ifxhcd_halt_status_e;
struct ifxhcd_urbd;
struct ifxhcd_hc ;
struct ifxhcd_epqh ;
struct ifxhcd_hcd;
/*!
\brief A URB Descriptor (URBD) holds the state of a bulk, control,
interrupt, or isochronous transfer. A single URBD is created for each URB
(of one of these types) submitted to the HCD. The transfer associated with
a URBD may require one or multiple transactions.
A URBD is linked to a EP Queue Head, which is entered in either the
isoc, intr or non-periodic schedule for execution. When a URBD is chosen for
execution, some or all of its transactions may be executed. After
execution, the state of the URBD is updated. The URBD may be retired if all
its transactions are complete or if an error occurred. Otherwise, it
remains in the schedule so more transactions can be executed later.
*/
typedef struct ifxhcd_urbd {
struct list_head urbd_list_entry; // Hook for EPQH->urbd_list and ifxhcd->urbd_complete_list
struct urb *urb; /*!< URB for this transfer */
//struct urb {
// struct list_head urb_list;
// struct list_head anchor_list;
// struct usb_anchor * anchor;
// struct usb_device * dev;
// struct usb_host_endpoint * ep;
// unsigned int pipe;
// int status;
// unsigned int transfer_flags;
// void * transfer_buffer;
// dma_addr_t transfer_dma;
// u32 transfer_buffer_length;
// u32 actual_length;
// unsigned char * setup_packet;
// dma_addr_t setup_dma;
// int start_frame;
// int number_of_packets;
// int interval;
// int error_count;
// void * context;
// usb_complete_t complete;
// struct usb_iso_packet_descriptor iso_frame_desc[0];
//};
//urb_list For use by current owner of the URB.
//anchor_list membership in the list of an anchor
//anchor to anchor URBs to a common mooring
//dev Identifies the USB device to perform the request.
//ep Points to the endpoint's data structure. Will
// eventually replace pipe.
//pipe Holds endpoint number, direction, type, and more.
// Create these values with the eight macros available; u
// sb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is
// "ctrl", "bulk", "int" or "iso". For example
// usb_sndbulkpipe or usb_rcvintpipe. Endpoint numbers
// range from zero to fifteen. Note that "in" endpoint two
// is a different endpoint (and pipe) from "out" endpoint
// two. The current configuration controls the existence,
// type, and maximum packet size of any given endpoint.
//status This is read in non-iso completion functions to get
// the status of the particular request. ISO requests
// only use it to tell whether the URB was unlinked;
// detailed status for each frame is in the fields of
// the iso_frame-desc.
//transfer_flags A variety of flags may be used to affect how URB
// submission, unlinking, or operation are handled.
// Different kinds of URB can use different flags.
// URB_SHORT_NOT_OK
// URB_ISO_ASAP
// URB_NO_TRANSFER_DMA_MAP
// URB_NO_SETUP_DMA_MAP
// URB_NO_FSBR
// URB_ZERO_PACKET
// URB_NO_INTERRUPT
//transfer_buffer This identifies the buffer to (or from) which the I/O
// request will be performed (unless URB_NO_TRANSFER_DMA_MAP
// is set). This buffer must be suitable for DMA; allocate it
// with kmalloc or equivalent. For transfers to "in"
// endpoints, contents of this buffer will be modified. This
// buffer is used for the data stage of control transfers.
//transfer_dma When transfer_flags includes URB_NO_TRANSFER_DMA_MAP, the
// device driver is saying that it provided this DMA address,
// which the host controller driver should use in preference
// to the transfer_buffer.
//transfer_buffer_length How big is transfer_buffer. The transfer may be broken
// up into chunks according to the current maximum packet size
// for the endpoint, which is a function of the configuration
// and is encoded in the pipe. When the length is zero, neither
// transfer_buffer nor transfer_dma is used.
//actual_length This is read in non-iso completion functions, and it tells
// how many bytes (out of transfer_buffer_length) were transferred.
// It will normally be the same as requested, unless either an error
// was reported or a short read was performed. The URB_SHORT_NOT_OK
// transfer flag may be used to make such short reads be reported
// as errors.
//setup_packet Only used for control transfers, this points to eight bytes of
// setup data. Control transfers always start by sending this data
// to the device. Then transfer_buffer is read or written, if needed.
//setup_dma For control transfers with URB_NO_SETUP_DMA_MAP set, the device
// driver has provided this DMA address for the setup packet. The
// host controller driver should use this in preference to setup_packet.
//start_frame Returns the initial frame for isochronous transfers.
//number_of_packets Lists the number of ISO transfer buffers.
//interval Specifies the polling interval for interrupt or isochronous transfers.
// The units are frames (milliseconds) for for full and low speed devices,
// and microframes (1/8 millisecond) for highspeed ones.
//error_count Returns the number of ISO transfers that reported errors.
//context For use in completion functions. This normally points to request-specific
// driver context.
//complete Completion handler. This URB is passed as the parameter to the completion
// function. The completion function may then do what it likes with the URB,
// including resubmitting or freeing it.
//iso_frame_desc[0] Used to provide arrays of ISO transfer buffers and to collect the transfer
// status for each buffer.
struct ifxhcd_epqh *epqh;
// Actual data portion, not SETUP or STATUS in case of CTRL XFER
// DMA adjusted
uint8_t *setup_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/
uint8_t *xfer_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/
uint32_t xfer_len; /*!< Total number of bytes to transfer in this xfer. */
unsigned is_in :1;
unsigned is_active:1;
// For ALL XFER
uint8_t error_count; /*!< Holds the number of bus errors that have occurred for a transaction
within this transfer.
*/
/*== AVM/BC 20101111 Needed for URB Complete List ==*/
int status;
// For ISOC XFER only
#ifdef __EN_ISOC__
int isoc_frame_index; /*!< Index of the next frame descriptor for an isochronous transfer. A
frame descriptor describes the buffer position and length of the
data to be transferred in the next scheduled (micro)frame of an
isochronous transfer. It also holds status for that transaction.
The frame index starts at 0.
*/
// For SPLITed ISOC XFER only
uint8_t isoc_split_pos; /*!< Position of the ISOC split on full/low speed */
uint16_t isoc_split_offset;/*!< Position of the ISOC split in the buffer for the current frame */
#endif
} ifxhcd_urbd_t;
/*!
\brief A EP Queue Head (EPQH) holds the static characteristics of an endpoint and
maintains a list of transfers (URBDs) for that endpoint. A EPQH structure may
be entered in either the isoc, intr or non-periodic schedule.
*/
typedef struct ifxhcd_epqh {
struct list_head epqh_list_entry; // Hook for EP Queues
struct list_head urbd_list; /*!< List of URBDs for this EPQH. */
struct ifxhcd_hc *hc; /*!< Host channel currently processing transfers for this EPQH. */
struct ifxhcd_urbd *urbd; /*!< URBD currently assigned to a host channel for this EPQH. */
struct usb_host_endpoint *sysep;
uint8_t ep_type; /*!< Endpoint type. One of the following values:
- IFXUSB_EP_TYPE_CTRL
- IFXUSB_EP_TYPE_ISOC
- IFXUSB_EP_TYPE_BULK
- IFXUSB_EP_TYPE_INTR
*/
uint16_t mps; /*!< wMaxPacketSize Field of Endpoint Descriptor. */
/* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/
/*uint8_t data_toggle;*/ /*!< Determines the PID of the next data packet
One of the following values:
- IFXHCD_HC_PID_DATA0
- IFXHCD_HC_PID_DATA1
*/
uint8_t is_active;
uint8_t pkt_count_limit;
#ifdef __EPQD_DESTROY_TIMEOUT__
struct timer_list destroy_timer;
#endif
uint16_t wait_for_sof;
uint8_t need_split; /*!< Full/low speed endpoint on high-speed hub requires split. */
uint16_t interval; /*!< Interval between transfers in (micro)frames. (for INTR)*/
uint16_t period_counter; /*!< Interval between transfers in (micro)frames. */
uint8_t period_do;
uint8_t aligned_checked;
#if defined(__UNALIGNED_BUFFER_ADJ__)
uint8_t using_aligned_setup;
uint8_t *aligned_setup;
uint8_t using_aligned_buf;
uint8_t *aligned_buf;
unsigned aligned_buf_len : 19;
#endif
uint8_t *dump_buf;
} ifxhcd_epqh_t;
#if defined(__HC_XFER_TIMEOUT__)
struct ifxusb_core_if;
struct ifxhcd_hc;
typedef struct hc_xfer_info
{
struct ifxusb_core_if *core_if;
struct ifxhcd_hc *hc;
} hc_xfer_info_t;
#endif //defined(__HC_XFER_TIMEOUT__)
/*!
\brief Host channel descriptor. This structure represents the state of a single
host channel when acting in host mode. It contains the data items needed to
transfer packets to an endpoint via a host channel.
*/
typedef struct ifxhcd_hc
{
struct list_head hc_list_entry ; // Hook to free hc
struct ifxhcd_epqh *epqh ; /*!< EP Queue Head for the transfer being processed by this channel. */
uint8_t hc_num ; /*!< Host channel number used for register address lookup */
uint8_t *xfer_buff ; /*!< Pointer to the entire transfer buffer. */
uint32_t xfer_count ; /*!< Number of bytes transferred so far. The offset of the begin of the buf */
uint32_t xfer_len ; /*!< Total number of bytes to transfer in this xfer. */
uint16_t start_pkt_count ; /*!< Packet count at start of transfer. Used to calculate the actual xfer size*/
ifxhcd_halt_status_e halt_status; /*!< Reason for halting the host channel. */
unsigned dev_addr : 7; /*!< Device to access */
unsigned ep_num : 4; /*!< EP to access */
unsigned is_in : 1; /*!< EP direction. 0: OUT, 1: IN */
unsigned speed : 2; /*!< EP speed. */
unsigned ep_type : 2; /*!< Endpoint type. */
unsigned mps :11; /*!< Max packet size in bytes */
unsigned data_pid_start : 2; /*!< PID for initial transaction. */
unsigned do_ping : 1; /*!< Set to 1 to indicate that a PING request should be issued on this
channel. If 0, process normally.
*/
unsigned xfer_started : 1; /*!< Flag to indicate whether the transfer has been started. Set to 1 if
it has been started, 0 otherwise.
*/
unsigned halting : 1; /*!< Set to 1 if the host channel has been halted, but the core is not
finished flushing queued requests. Otherwise 0.
*/
unsigned short_rw : 1; /*!< When Tx, means termination needed.
When Rx, indicate Short Read */
/* Split settings for the host channel */
unsigned split : 2; /*!< Split: 0-Non Split, 1-SSPLIT, 2&3 CSPLIT */
/*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/
unsigned nyet_count;
/* nak monitor */
unsigned nak_retry_r : 16;
unsigned nak_retry : 16;
#define nak_retry_max 40000
unsigned nak_countdown : 8;
unsigned nak_countdown_r: 8;
#define nak_countdown_max 1
uint16_t wait_for_sof;
ifxhcd_control_phase_e control_phase; /*!< Current phase for control transfers (Setup, Data, or Status). */
uint32_t ssplit_out_xfer_count; /*!< How many bytes transferred during SSPLIT OUT */
#ifdef __DEBUG__
uint32_t start_hcchar_val;
#endif
#ifdef __HC_XFER_TIMEOUT__
hc_xfer_info_t hc_xfer_info;
struct timer_list hc_xfer_timer;
#endif
uint32_t hcchar;
/* Split settings for the host channel */
uint8_t hub_addr; /*!< Address of high speed hub */
uint8_t port_addr; /*!< Port of the low/full speed device */
#ifdef __EN_ISOC__
uint8_t isoc_xact_pos; /*!< Split transaction position */
#endif
} ifxhcd_hc_t;
/*!
\brief This structure holds the state of the HCD, including the non-periodic and
periodic schedules.
*/
typedef struct ifxhcd_hcd
{
struct device *dev;
struct hc_driver hc_driver;
ifxusb_core_if_t core_if; /*!< Pointer to the core interface structure. */
struct usb_hcd *syshcd;
volatile union ifxhcd_internal_flags
{
uint32_t d32;
struct
{
unsigned port_connect_status_change : 1;
unsigned port_connect_status : 1;
unsigned port_reset_change : 1;
unsigned port_enable_change : 1;
unsigned port_suspend_change : 1;
unsigned port_over_current_change : 1;
unsigned reserved : 27;
} b;
} flags; /*!< Internal HCD Flags */
struct ifxhcd_hc ifxhc[MAX_EPS_CHANNELS]; /*!< Array of pointers to the host channel descriptors. Allows accessing
a host channel descriptor given the host channel number. This is
useful in interrupt handlers.
*/
struct list_head free_hc_list; /*!< Free host channels in the controller. This is a list of ifxhcd_hc_t items. */
uint8_t *status_buf; /*!< Buffer to use for any data received during the status phase of a
control transfer. Normally no data is transferred during the status
phase. This buffer is used as a bit bucket.
*/
#define IFXHCD_STATUS_BUF_SIZE 64
struct list_head epqh_np_active; // with URBD, with HC
struct list_head epqh_np_ready; // with URBD, No HC
struct list_head epqh_intr_active; // with URBD, with HC
struct list_head epqh_intr_ready; // with URBD, no pass, No HC
#ifdef __EN_ISOC__
struct list_head epqh_isoc_active; // with URBD, with HC
struct list_head epqh_isoc_ready; // with URBD, no pass, No HC
#endif
/*== AVM/BC 20101111 URB Complete List ==*/
struct list_head urbd_complete_list;
struct list_head epqh_stdby;
/* AVM/BC 20101111 flags removed */
//unsigned process_channels_in_use : 1;
//unsigned select_eps_in_use : 1;
struct tasklet_struct select_eps; /*!< Tasket to do a reset */
uint32_t lastframe;
spinlock_t lock;
#ifdef __USE_TIMER_4_SOF__
struct hrtimer hr_timer;
#endif
} ifxhcd_hcd_t;
/* Gets the ifxhcd_hcd from a struct usb_hcd */
static inline ifxhcd_hcd_t *syshcd_to_ifxhcd(struct usb_hcd *syshcd)
{
return (ifxhcd_hcd_t *)(syshcd->hcd_priv[0]);
}
/* Gets the struct usb_hcd that contains a ifxhcd_hcd_t. */
static inline struct usb_hcd *ifxhcd_to_syshcd(ifxhcd_hcd_t *ifxhcd)
{
return (struct usb_hcd *)(ifxhcd->syshcd);
}
/*! \brief HCD Create/Destroy Functions */
/*@{*/
extern int ifxhcd_init (ifxhcd_hcd_t *_ifxhcd);
extern void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd);
/*@}*/
/*! \brief Linux HC Driver API Functions */
/*@{*/
extern int ifxhcd_start(struct usb_hcd *hcd);
extern void ifxhcd_stop (struct usb_hcd *hcd);
extern int ifxhcd_get_frame_number(struct usb_hcd *hcd);
/*!
\brief This function does the setup for a data transfer for a host channel and
starts the transfer. May be called in either Slave mode or DMA mode. In
Slave mode, the caller must ensure that there is sufficient space in the
request queue and Tx Data FIFO.
For an OUT transfer in Slave mode, it loads a data packet into the
appropriate FIFO. If necessary, additional data packets will be loaded in
the Host ISR.
For an IN transfer in Slave mode, a data packet is requested. The data
packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
additional data packets are requested in the Host ISR.
For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
register along with a packet count of 1 and the channel is enabled. This
causes a single PING transaction to occur. Other fields in HCTSIZ are
simply set to 0 since no data transfer occurs in this case.
For a PING transfer in DMA mode, the HCTSIZ register is initialized with
all the information required to perform the subsequent data transfer. In
addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
controller performs the entire PING protocol, then starts the data
transfer.
@param _ifxhc Information needed to initialize the host channel. The xfer_len
value may be reduced to accommodate the max widths of the XferSize and
PktCnt fields in the HCTSIZn register. The multi_count value may be changed
to reflect the final xfer_len value.
*/
extern void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
//extern int ifxhcd_urb_enqueue(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep, struct urb *_urb, gfp_t mem_flags);
//extern int ifxhcd_urb_dequeue(struct usb_hcd *_syshcd, struct urb *_urb);
extern irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd);
int ifxhcd_urb_enqueue( struct usb_hcd *_syshcd,
/*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/
struct urb *_urb,
gfp_t _mem_flags);
int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd,
struct urb *_urb, int status /* Parameter neu in 2.6.28 */);
extern void ifxhcd_endpoint_disable(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep);
extern int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf);
extern int ifxhcd_hub_control( struct usb_hcd *_syshcd,
u16 _typeReq,
u16 _wValue,
u16 _wIndex,
char *_buf,
u16 _wLength);
/*@}*/
/*! \brief Transaction Execution Functions */
/*@{*/
extern void ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status);
/*@}*/
/*! \brief Deferred Transaction Execution Functions */
/*@{*/
/*== AVM/BC 20101111 URB Complete List ==*/
extern void defer_ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status);
/*!
\brief Clears the transfer state for a host channel. This function is normally
called after a transfer is done and the host channel is being released.
*/
extern void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
/*!
\brief Attempts to halt a host channel. This function should only be called in
Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
normal circumstances in DMA mode, the controller halts the channel when the
transfer is complete or a condition occurs that requires application
intervention.
In slave mode, checks for a free request queue entry, then sets the Channel
Enable and Channel Disable bits of the Host Channel Characteristics
register of the specified channel to intiate the halt. If there is no free
request queue entry, sets only the Channel Disable bit of the HCCHARn
register to flush requests for this channel. In the latter case, sets a
flag to indicate that the host channel needs to be halted when a request
queue slot is open.
In DMA mode, always sets the Channel Enable and Channel Disable bits of the
HCCHARn register. The controller ensures there is space in the request
queue before submitting the halt request.
Some time may elapse before the core flushes any posted requests for this
host channel and halts. The Channel Halted interrupt handler completes the
deactivation of the host channel.
*/
extern void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if,
ifxhcd_hc_t *_ifxhc,
ifxhcd_halt_status_e _halt_status);
/*!
\brief Prepares a host channel for transferring packets to/from a specific
endpoint. The HCCHARn register is set up with the characteristics specified
in _ifxhc. Host channel interrupts that may need to be serviced while this
transfer is in progress are enabled.
*/
extern void ifxhcd_hc_init(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
/*!
\brief This function is called to handle the disconnection of host port.
*/
int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd);
/*@}*/
/*! \brief Interrupt Handler Functions */
/*@{*/
extern irqreturn_t ifxhcd_oc_irq(int _irq, void *_dev);
extern int32_t ifxhcd_handle_oc_intr(ifxhcd_hcd_t *_ifxhcd);
extern int32_t ifxhcd_handle_intr (ifxhcd_hcd_t *_ifxhcd);
/*@}*/
/*! \brief Schedule Queue Functions */
/*@{*/
extern ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb);
extern void ifxhcd_epqh_free ( ifxhcd_epqh_t *_epqh);
extern void select_eps (ifxhcd_hcd_t *_ifxhcd);
extern void process_channels(ifxhcd_hcd_t *_ifxhcd);
extern void process_channels_sub(ifxhcd_hcd_t *_ifxhcd);
extern void complete_channel(ifxhcd_hcd_t *_ifxhcd, ifxhcd_hc_t *_ifxhc, ifxhcd_urbd_t *_urbd);
extern void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
extern void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
extern void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
extern void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh);
extern int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb);
/*@}*/
/*! \brief Gets the usb_host_endpoint associated with an URB. */
static inline struct usb_host_endpoint *ifxhcd_urb_to_endpoint(struct urb *_urb)
{
struct usb_device *dev = _urb->dev;
int ep_num = usb_pipeendpoint(_urb->pipe);
return (usb_pipein(_urb->pipe))?(dev->ep_in[ep_num]):(dev->ep_out[ep_num]);
}
/*!
* \brief Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
* qualified with its direction (possible 32 endpoints per device).
*/
#define ifxhcd_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
/* AVM/WK: not needed?
extern struct usb_device *usb_alloc_dev (struct usb_device *parent, struct usb_bus *, unsigned port);
extern int usb_add_hcd (struct usb_hcd *syshcd, unsigned int irqnum, unsigned long irqflags);
extern void usb_remove_hcd (struct usb_hcd *syshcd);
extern struct usb_hcd *usb_create_hcd (const struct hc_driver *driver, struct device *dev, char *bus_name);
extern void usb_hcd_giveback_urb (struct usb_hcd *syshcd, struct urb *urb);
extern void usb_put_hcd (struct usb_hcd *syshcd);
extern long usb_calc_bus_time (int speed, int is_input, int isoc, int bytecount);
*/
/** Internal Functions */
void ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd);
extern char *syserr(int errno);
/*@}*//*IFXUSB_HCD*/
#endif // __IFXHCD_H__

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target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_es.c Normal file
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@ -0,0 +1,549 @@
/*****************************************************************************
** FILE NAME : ifxhcd_es.c
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : The file contain function to enable host mode USB-IF Electrical Test function.
*****************************************************************************/
/*!
\file ifxhcd_es.c
\ingroup IFXUSB_DRIVER_V3
\brief The file contain function to enable host mode USB-IF Electrical Test function.
*/
#include <linux/version.h>
#include "ifxusb_version.h"
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/dma-mapping.h>
#include "ifxusb_plat.h"
#include "ifxusb_regs.h"
#include "ifxusb_cif.h"
#include "ifxhcd.h"
#ifdef __WITH_HS_ELECT_TST__
/*
* Quick and dirty hack to implement the HS Electrical Test
* SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
*
* This code was copied from our userspace app "hset". It sends a
* Get Device Descriptor control sequence in two parts, first the
* Setup packet by itself, followed some time later by the In and
* Ack packets. Rather than trying to figure out how to add this
* functionality to the normal driver code, we just hijack the
* hardware, using these two function to drive the hardware
* directly.
*/
void do_setup(ifxusb_core_if_t *_core_if)
{
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0];
uint32_t *data_fifo = _core_if->data_fifo[0];
gint_data_t gintsts;
hctsiz_data_t hctsiz;
hcchar_data_t hcchar;
haint_data_t haint;
hcint_data_t hcint;
/* Enable HAINTs */
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
/* Enable HCINTs */
ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/*
* Send Setup packet (Get Device Descriptor)
*/
/* Make sure channel is disabled */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
if (hcchar.b.chen) {
//fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
hcchar.b.chdis = 1;
// hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
//sleep(1);
mdelay(1000);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//if (hcchar.b.chen) {
// fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
//}
}
/* Set HCTSIZ */
hctsiz.d32 = 0;
hctsiz.b.xfersize = 8;
hctsiz.b.pktcnt = 1;
hctsiz.b.pid = IFXUSB_HC_PID_SETUP;
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
/* Set HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
hcchar.b.epdir = 0;
hcchar.b.epnum = 0;
hcchar.b.mps = 8;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
/* Fill FIFO with Setup data for Get Device Descriptor */
ifxusb_wreg(data_fifo++, 0x01000680);
ifxusb_wreg(data_fifo++, 0x00080000);
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
/* Wait for host channel interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.hcintr == 0);
//fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
/* Disable HCINTs */
ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
/* Disable HAINTs */
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
}
void do_in_ack(ifxusb_core_if_t *_core_if)
{
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0];
uint32_t *data_fifo = _core_if->data_fifo[0];
gint_data_t gintsts;
hctsiz_data_t hctsiz;
hcchar_data_t hcchar;
haint_data_t haint;
hcint_data_t hcint;
grxsts_data_t grxsts;
/* Enable HAINTs */
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
/* Enable HCINTs */
ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/*
* Receive Control In packet
*/
/* Make sure channel is disabled */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
if (hcchar.b.chen) {
//fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
hcchar.b.chdis = 1;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
//sleep(1);
mdelay(1000);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//if (hcchar.b.chen) {
// fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
//}
}
/* Set HCTSIZ */
hctsiz.d32 = 0;
hctsiz.b.xfersize = 8;
hctsiz.b.pktcnt = 1;
hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
/* Set HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
hcchar.b.epdir = 1;
hcchar.b.epnum = 0;
hcchar.b.mps = 8;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
/* Wait for receive status queue interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.rxstsqlvl == 0);
//fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
/* Read RXSTS */
grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
/* Clear RXSTSQLVL in GINTSTS */
gintsts.d32 = 0;
gintsts.b.rxstsqlvl = 1;
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
switch (grxsts.hb.pktsts) {
case IFXUSB_HSTS_DATA_UPDT:
/* Read the data into the host buffer */
if (grxsts.hb.bcnt > 0) {
int i;
int word_count = (grxsts.hb.bcnt + 3) / 4;
for (i = 0; i < word_count; i++) {
(void)ifxusb_rreg(data_fifo++);
}
}
//fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.hb.bcnt);
break;
default:
//fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
break;
}
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
/* Wait for receive status queue interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.rxstsqlvl == 0);
//fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
/* Read RXSTS */
grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
/* Clear RXSTSQLVL in GINTSTS */
gintsts.d32 = 0;
gintsts.b.rxstsqlvl = 1;
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
switch (grxsts.hb.pktsts) {
case IFXUSB_HSTS_XFER_COMP:
break;
default:
//fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
break;
}
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
/* Wait for host channel interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.hcintr == 0);
//fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
// usleep(100000);
// mdelay(100);
mdelay(1);
/*
* Send handshake packet
*/
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Make sure channel is disabled */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
if (hcchar.b.chen) {
//fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
hcchar.b.chdis = 1;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
//sleep(1);
mdelay(1000);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//if (hcchar.b.chen) {
// fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
//}
}
/* Set HCTSIZ */
hctsiz.d32 = 0;
hctsiz.b.xfersize = 0;
hctsiz.b.pktcnt = 1;
hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
/* Set HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
hcchar.b.epdir = 0;
hcchar.b.epnum = 0;
hcchar.b.mps = 8;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
/* Wait for host channel interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.hcintr == 0);
//fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
/* Disable HCINTs */
ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
/* Disable HAINTs */
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
}
#endif //__WITH_HS_ELECT_TST__

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/*****************************************************************************
** FILE NAME : ifxhcd_queue.c
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : This file contains the functions to manage Queue Heads and Queue
** Transfer Descriptors.
*****************************************************************************/
/*!
\file ifxhcd_queue.c
\ingroup IFXUSB_DRIVER_V3
\brief This file contains the functions to manage Queue Heads and Queue
Transfer Descriptors.
*/
#include <linux/version.h>
#include "ifxusb_version.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include "ifxusb_plat.h"
#include "ifxusb_regs.h"
#include "ifxusb_cif.h"
#include "ifxhcd.h"
#ifdef __EPQD_DESTROY_TIMEOUT__
#define epqh_self_destroy_timeout 5
static void eqph_destroy_func(unsigned long _ptr)
{
ifxhcd_epqh_t *epqh=(ifxhcd_epqh_t *)_ptr;
if(epqh)
{
ifxhcd_epqh_free (epqh);
}
}
#endif
#define SCHEDULE_SLOP 10
/*!
\brief This function allocates and initializes a EPQH.
\param _ifxhcd The HCD state structure for the USB Host controller.
\param[in] _urb Holds the information about the device/endpoint that we need
to initialize the EPQH.
\return Returns pointer to the newly allocated EPQH, or NULL on error.
*/
ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb)
{
ifxhcd_epqh_t *epqh;
hprt0_data_t hprt0;
struct usb_host_endpoint *sysep = ifxhcd_urb_to_endpoint(_urb);
/* Allocate memory */
// epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_KERNEL);
epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_ATOMIC);
if(epqh == NULL)
return NULL;
memset (epqh, 0, sizeof (ifxhcd_epqh_t));
epqh->sysep=sysep;
/* Initialize EPQH */
switch (usb_pipetype(_urb->pipe))
{
case PIPE_CONTROL : epqh->ep_type = IFXUSB_EP_TYPE_CTRL; break;
case PIPE_BULK : epqh->ep_type = IFXUSB_EP_TYPE_BULK; break;
case PIPE_ISOCHRONOUS: epqh->ep_type = IFXUSB_EP_TYPE_ISOC; break;
case PIPE_INTERRUPT : epqh->ep_type = IFXUSB_EP_TYPE_INTR; break;
}
//epqh->data_toggle = IFXUSB_HC_PID_DATA0;
epqh->mps = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if);
INIT_LIST_HEAD(&epqh->urbd_list);
INIT_LIST_HEAD(&epqh->epqh_list_entry);
epqh->hc = NULL;
epqh->dump_buf = ifxusb_alloc_buf(epqh->mps, 0);
/* FS/LS Enpoint on HS Hub
* NOT virtual root hub */
epqh->need_split = 0;
epqh->pkt_count_limit=0;
if(epqh->ep_type == IFXUSB_EP_TYPE_BULK && !(usb_pipein(_urb->pipe)) )
epqh->pkt_count_limit=4;
if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED &&
((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)) &&
(_urb->dev->tt) && (_urb->dev->tt->hub->devnum != 1))
{
IFX_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
_urb->dev->ttport);
epqh->need_split = 1;
epqh->pkt_count_limit=1;
}
if (epqh->ep_type == IFXUSB_EP_TYPE_INTR ||
epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
{
/* Compute scheduling parameters once and save them. */
epqh->interval = _urb->interval;
if(epqh->need_split)
epqh->interval *= 8;
}
epqh->period_counter=0;
epqh->is_active=0;
#ifdef __EPQD_DESTROY_TIMEOUT__
/* Start a timer for this transfer. */
init_timer(&epqh->destroy_timer);
epqh->destroy_timer.function = eqph_destroy_func;
epqh->destroy_timer.data = (unsigned long)(epqh);
#endif
#ifdef __DEBUG__
IFX_DEBUGPL(DBG_HCD , "IFXUSB HCD EPQH Initialized\n");
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - epqh = %p\n", epqh);
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Device Address = %d EP %d, %s\n",
_urb->dev->devnum,
usb_pipeendpoint(_urb->pipe),
usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Speed = %s\n",
({ char *speed; switch (_urb->dev->speed) {
case USB_SPEED_LOW: speed = "low" ; break;
case USB_SPEED_FULL: speed = "full"; break;
case USB_SPEED_HIGH: speed = "high"; break;
default: speed = "?"; break;
}; speed;}));
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Type = %s\n",
({
char *type; switch (epqh->ep_type)
{
case IFXUSB_EP_TYPE_ISOC: type = "isochronous"; break;
case IFXUSB_EP_TYPE_INTR: type = "interrupt" ; break;
case IFXUSB_EP_TYPE_CTRL: type = "control" ; break;
case IFXUSB_EP_TYPE_BULK: type = "bulk" ; break;
default: type = "?"; break;
};
type;
}));
if (epqh->ep_type == IFXUSB_EP_TYPE_INTR)
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - interval = %d\n", epqh->interval);
#endif
return epqh;
}
/*!
\brief Free the EPQH. EPQH should already be removed from a list.
URBD list should already be empty if called from URB Dequeue.
\param[in] _epqh The EPQH to free.
*/
void ifxhcd_epqh_free (ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
if(_epqh->sysep) _epqh->sysep->hcpriv=NULL;
_epqh->sysep=NULL;
if(!_epqh)
return;
/* Free each QTD in the QTD list */
local_irq_save (flags);
if (!list_empty(&_epqh->urbd_list))
IFX_WARN("%s() invalid epqh state\n",__func__);
#if defined(__UNALIGNED_BUFFER_ADJ__)
if(_epqh->aligned_buf)
ifxusb_free_buf(_epqh->aligned_buf);
if(_epqh->aligned_setup)
ifxusb_free_buf(_epqh->aligned_setup);
#endif
if (!list_empty(&_epqh->epqh_list_entry))
list_del_init(&_epqh->epqh_list_entry);
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
#endif
if(_epqh->dump_buf)
ifxusb_free_buf(_epqh->dump_buf);
_epqh->dump_buf=0;
kfree (_epqh);
local_irq_restore (flags);
}
/*!
\brief This function adds a EPQH to
\return 0 if successful, negative error code otherwise.
*/
void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_epqh->epqh_list_entry))
{
#ifdef __EN_ISOC__
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
else
#endif
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
else
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
_epqh->is_active=0;
}
else if(!_epqh->is_active)
{
#ifdef __EN_ISOC__
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
else
#endif
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
else
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
}
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
#endif
local_irq_restore(flags);
}
void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_epqh->epqh_list_entry))
IFX_WARN("%s() invalid epqh state\n",__func__);
#ifdef __EN_ISOC__
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active);
else
#endif
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active);
else
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_active);
_epqh->is_active=1;
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
#endif
local_irq_restore(flags);
}
void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_epqh->urbd_list))
{
if(_epqh->ep_type == IFXUSB_EP_TYPE_ISOC || _epqh->ep_type == IFXUSB_EP_TYPE_INTR)
{
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_stdby);
}
else
{
list_del_init(&_epqh->epqh_list_entry);
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
_epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout);
add_timer(&_epqh->destroy_timer );
#endif
}
}
else
{
#ifdef __EN_ISOC__
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
else
#endif
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
else
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
}
_epqh->is_active=0;
local_irq_restore(flags);
}
void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
if(_epqh->ep_type != IFXUSB_EP_TYPE_ISOC && _epqh->ep_type != IFXUSB_EP_TYPE_INTR)
return;
local_irq_save(flags);
if (list_empty(&_epqh->epqh_list_entry))
IFX_WARN("%s() invalid epqh state\n",__func__);
if (!list_empty(&_epqh->urbd_list))
IFX_WARN("%s() invalid epqh state(not empty)\n",__func__);
_epqh->is_active=0;
list_del_init(&_epqh->epqh_list_entry);
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
_epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout);
add_timer(&_epqh->destroy_timer );
#endif
local_irq_restore(flags);
}
int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb)
{
ifxhcd_urbd_t *urbd;
struct usb_host_endpoint *sysep;
ifxhcd_epqh_t *epqh;
unsigned long flags;
/* == AVM/WK 20100714 retval correctly initialized ==*/
int retval = -ENOMEM;
/*== AVM/BC 20100630 - Spinlock ==*/
//local_irq_save(flags);
SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
// urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_KERNEL);
urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_ATOMIC);
if (urbd != NULL) /* Initializes a QTD structure.*/
{
retval = 0;
memset (urbd, 0, sizeof (ifxhcd_urbd_t));
sysep = ifxhcd_urb_to_endpoint(_urb);
epqh = (ifxhcd_epqh_t *)sysep->hcpriv;
if (epqh == NULL)
{
epqh = ifxhcd_epqh_create (_ifxhcd, _urb);
if (epqh == NULL)
{
retval = -ENOSPC;
kfree(urbd);
//local_irq_restore (flags);
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
return retval;
}
sysep->hcpriv = epqh;
}
INIT_LIST_HEAD(&urbd->urbd_list_entry);
/*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/
retval = usb_hcd_link_urb_to_ep(ifxhcd_to_syshcd(_ifxhcd), _urb);
if (unlikely(retval)){
kfree(urbd);
kfree(epqh);
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
return retval;
}
list_add_tail(&urbd->urbd_list_entry, &epqh->urbd_list);
urbd->urb = _urb;
_urb->hcpriv = urbd;
urbd->epqh=epqh;
urbd->is_in=usb_pipein(_urb->pipe) ? 1 : 0;;
urbd->xfer_len=_urb->transfer_buffer_length;
#define URB_NO_SETUP_DMA_MAP 0
if(urbd->xfer_len>0)
{
if(_urb->transfer_flags && URB_NO_TRANSFER_DMA_MAP)
urbd->xfer_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->transfer_dma));
else
urbd->xfer_buff = (uint8_t *) _urb->transfer_buffer;
}
if(epqh->ep_type == IFXUSB_EP_TYPE_CTRL)
{
if(_urb->transfer_flags && URB_NO_SETUP_DMA_MAP)
urbd->setup_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->setup_dma));
else
urbd->setup_buff = (uint8_t *) _urb->setup_packet;
}
}
//local_irq_restore (flags);
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
return retval;
}

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/*****************************************************************************
** FILE NAME : ifxusb_cif.h
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : The Core Interface provides basic services for accessing and
** managing the IFX USB hardware. These services are used by both the
** Host Controller Driver and the Peripheral Controller Driver.
** FUNCTIONS :
** COMPILER : gcc
** REFERENCE : IFX hardware ref handbook for each plateforms
** COPYRIGHT :
** Version Control Section **
** $Author$
** $Date$
** $Revisions$
** $Log$ Revision history
*****************************************************************************/
/*!
\defgroup IFXUSB_DRIVER_V3 IFX USB SS Project
\brief IFX USB subsystem V3.x
*/
/*!
\defgroup IFXUSB_CIF Core Interface APIs
\ingroup IFXUSB_DRIVER_V3
\brief The Core Interface provides basic services for accessing and
managing the IFXUSB hardware. These services are used by both the
Host Controller Driver and the Peripheral Controller Driver.
*/
/*!
\file ifxusb_cif.h
\ingroup IFXUSB_DRIVER_V3
\brief This file contains the interface to the IFX USB Core.
*/
#if !defined(__IFXUSB_CIF_H__)
#define __IFXUSB_CIF_H__
#include <linux/workqueue.h>
#include <linux/version.h>
#include <asm/param.h>
#include "ifxusb_plat.h"
#include "ifxusb_regs.h"
#ifdef __DEBUG__
#include "linux/timer.h"
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define IFXUSB_PARAM_SPEED_HIGH 0
#define IFXUSB_PARAM_SPEED_FULL 1
#define IFXUSB_EP_SPEED_LOW 0
#define IFXUSB_EP_SPEED_FULL 1
#define IFXUSB_EP_SPEED_HIGH 2
#define IFXUSB_EP_TYPE_CTRL 0
#define IFXUSB_EP_TYPE_ISOC 1
#define IFXUSB_EP_TYPE_BULK 2
#define IFXUSB_EP_TYPE_INTR 3
#define IFXUSB_HC_PID_DATA0 0
#define IFXUSB_HC_PID_DATA2 1
#define IFXUSB_HC_PID_DATA1 2
#define IFXUSB_HC_PID_MDATA 3
#define IFXUSB_HC_PID_SETUP 3
/*!
\addtogroup IFXUSB_CIF
*/
/*@{*/
/*!
\struct ifxusb_params
\brief IFXUSB Parameters structure.
This structure is used for both importing from insmod stage and run-time storage.
These parameters define how the IFXUSB controller should be configured.
*/
typedef struct ifxusb_params
{
int32_t dma_burst_size; /*!< The DMA Burst size (applicable only for Internal DMA
Mode). 0(for single), 1(incr), 4(incr4), 8(incr8) 16(incr16)
*/
/* Translate this to GAHBCFG values */
int32_t speed; /*!< Specifies the maximum speed of operation in host and device mode.
The actual speed depends on the speed of the attached device and
the value of phy_type. The actual speed depends on the speed of the
attached device.
0 - High Speed (default)
1 - Full Speed
*/
int32_t data_fifo_size; /*!< Total number of dwords in the data FIFO memory. This
memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
Tx FIFOs.
32 to 32768
*/
#ifdef __IS_DEVICE__
int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in device mode.
16 to 32768
*/
int32_t tx_fifo_size[MAX_EPS_CHANNELS]; /*!< Number of dwords in each of the Tx FIFOs in device mode.
4 to 768
*/
#ifdef __DED_FIFO__
int32_t thr_ctl; /*!< Threshold control on/off */
int32_t tx_thr_length; /*!< Threshold length for Tx */
int32_t rx_thr_length; /*!< Threshold length for Rx*/
#endif
#else //__IS_HOST__
int32_t host_channels; /*!< The number of host channel registers to use.
1 to 16
*/
int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in host mode.
16 to 32768
*/
int32_t nperio_tx_fifo_size;/*!< Number of dwords in the non-periodic Tx FIFO in host mode.
16 to 32768
*/
int32_t perio_tx_fifo_size; /*!< Number of dwords in the host periodic Tx FIFO.
16 to 32768
*/
#endif //__IS_HOST__
int32_t max_transfer_size; /*!< The maximum transfer size supported in bytes.
2047 to 65,535
*/
int32_t max_packet_count; /*!< The maximum number of packets in a transfer.
15 to 511 (default 511)
*/
int32_t phy_utmi_width; /*!< Specifies the UTMI+ Data Width.
8 or 16 bits (default 16)
*/
int32_t turn_around_time_hs; /*!< Specifies the Turn-Around time at HS*/
int32_t turn_around_time_fs; /*!< Specifies the Turn-Around time at FS*/
int32_t timeout_cal_hs; /*!< Specifies the Timeout_Calibration at HS*/
int32_t timeout_cal_fs; /*!< Specifies the Timeout_Calibration at FS*/
} ifxusb_params_t;
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/*!
\struct ifxusb_core_if
\brief The ifx_core_if structure contains information needed to manage
the IFX USB controller acting in either host or device mode. It
represents the programming view of the controller as a whole.
*/
typedef struct ifxusb_core_if
{
ifxusb_params_t params; /*!< Run-time Parameters */
uint8_t core_no; /*!< core number (used as id when multi-core case */
char *core_name; /*!< core name used for registration and informative purpose*/
int irq; /*!< irq number this core is hooked */
/*****************************************************************
* Structures and pointers to physical register interface.
*****************************************************************/
/** Core Global registers starting at offset 000h. */
ifxusb_core_global_regs_t *core_global_regs; /*!< pointer to Core Global Registers, offset at 000h */
/** Host-specific registers */
#ifdef __IS_HOST__
/** Host Global Registers starting at offset 400h.*/
ifxusb_host_global_regs_t *host_global_regs; /*!< pointer to Host Global Registers, offset at 400h */
#define IFXUSB_HOST_GLOBAL_REG_OFFSET 0x400
/** Host Port 0 Control and Status Register */
volatile uint32_t *hprt0; /*!< pointer to HPRT0 Registers, offset at 440h */
#define IFXUSB_HOST_PORT_REGS_OFFSET 0x440
/** Host Channel Specific Registers at offsets 500h-5FCh. */
ifxusb_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; /*!< pointer to Host-Channel n Registers, offset at 500h */
#define IFXUSB_HOST_CHAN_REGS_OFFSET 0x500
#define IFXUSB_CHAN_REGS_OFFSET 0x20
#endif
/** Device-specific registers */
#ifdef __IS_DEVICE__
/** Device Global Registers starting at offset 800h */
ifxusb_device_global_regs_t *dev_global_regs; /*!< pointer to Device Global Registers, offset at 800h */
#define IFXUSB_DEV_GLOBAL_REG_OFFSET 0x800
/** Device Logical IN Endpoint-Specific Registers 900h-AFCh */
ifxusb_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; /*!< pointer to Device IN-EP Registers, offset at 900h */
#define IFXUSB_DEV_IN_EP_REG_OFFSET 0x900
#define IFXUSB_EP_REG_OFFSET 0x20
/** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
ifxusb_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];/*!< pointer to Device OUT-EP Registers, offset at 900h */
#define IFXUSB_DEV_OUT_EP_REG_OFFSET 0xB00
#endif
/** Power and Clock Gating Control Register */
volatile uint32_t *pcgcctl; /*!< pointer to Power and Clock Gating Control Registers, offset at E00h */
#define IFXUSB_PCGCCTL_OFFSET 0xE00
/** Push/pop addresses for endpoints or host channels.*/
uint32_t *data_fifo[MAX_EPS_CHANNELS]; /*!< pointer to FIFO access windows, offset at 1000h */
#define IFXUSB_DATA_FIFO_OFFSET 0x1000
#define IFXUSB_DATA_FIFO_SIZE 0x1000
uint32_t *data_fifo_dbg; /*!< pointer to FIFO debug windows, offset at 1000h */
/** Hardware Configuration -- stored here for convenience.*/
hwcfg1_data_t hwcfg1; /*!< preserved Hardware Configuration 1 */
hwcfg2_data_t hwcfg2; /*!< preserved Hardware Configuration 2 */
hwcfg3_data_t hwcfg3; /*!< preserved Hardware Configuration 3 */
hwcfg4_data_t hwcfg4; /*!< preserved Hardware Configuration 3 */
uint32_t snpsid; /*!< preserved SNPSID */
/*****************************************************************
* Run-time informations.
*****************************************************************/
/* Set to 1 if the core PHY interface bits in USBCFG have been initialized. */
uint8_t phy_init_done; /*!< indicated PHY is initialized. */
#ifdef __IS_HOST__
uint8_t queuing_high_bandwidth; /*!< Host mode, Queueing High Bandwidth. */
#endif
} ifxusb_core_if_t;
/*@}*//*IFXUSB_CIF*/
/*!
\fn void *ifxusb_alloc_buf(size_t size, int clear)
\brief This function is called to allocate buffer of specified size.
The allocated buffer is mapped into DMA accessable address.
\param size Size in BYTE to be allocated
\param clear 0: don't do clear after buffer allocated, other: do clear to zero
\return 0/NULL: Fail; uncached pointer of allocated buffer
\ingroup IFXUSB_CIF
*/
extern void *ifxusb_alloc_buf(size_t size, int clear);
/*!
\fn void ifxusb_free_buf(void *vaddr)
\brief This function is called to free allocated buffer.
\param vaddr the uncached pointer of the buffer
\ingroup IFXUSB_CIF
*/
extern void ifxusb_free_buf(void *vaddr);
/*!
\fn int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
int _irq,
uint32_t _reg_base_addr,
uint32_t _fifo_base_addr,
uint32_t _fifo_dbg_addr)
\brief This function is called to initialize the IFXUSB CSR data
structures. The register addresses in the device and host
structures are initialized from the base address supplied by the
caller. The calling function must make the OS calls to get the
base address of the IFXUSB controller registers.
\param _core_if Pointer of core_if structure
\param _irq irq number
\param _reg_base_addr Base address of IFXUSB core registers
\param _fifo_base_addr Fifo base address
\param _fifo_dbg_addr Fifo debug address
\return 0: success;
\ingroup IFXUSB_CIF
*/
extern int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
int _irq,
uint32_t _reg_base_addr,
uint32_t _fifo_base_addr,
uint32_t _fifo_dbg_addr);
/*!
\fn void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if)
\brief This function free the mapped address in the IFXUSB CSR data structures.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if )
\brief This function enbles the controller's Global Interrupt in the AHB Config register.
\param _core_if Pointer of core_if structure
*/
extern void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if );
/*!
\fn void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if )
\brief This function disables the controller's Global Interrupt in the AHB Config register.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if );
/*!
\fn void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num )
\brief Flush a Tx FIFO.
\param _core_if Pointer of core_if structure
\param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO )
\ingroup IFXUSB_CIF
*/
extern void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num );
/*!
\fn void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if )
\brief Flush Rx FIFO.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if );
/*!
\fn void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if )
\brief Flush ALL Rx and Tx FIFO.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if );
/*!
\fn int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if)
\brief Do core a soft reset of the core. Be careful with this because it
resets all the internal state machines of the core.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if);
/*!
\brief Turn on the USB Core Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_power_on (ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_power_off (ifxusb_core_if_t *_core_if)
\brief Turn off the USB Core Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_power_off (ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if)
\brief Turn on the USB PHY Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if)
\brief Turn off the USB PHY Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_hard_reset(ifxusb_core_if_t *_core_if)
\brief Reset on the USB Core RCU
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_hard_reset(ifxusb_core_if_t *_core_if);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef __IS_HOST__
/*!
\fn void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
\brief This function initializes the IFXUSB controller registers for Host mode.
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
request queues.
\param _core_if Pointer of core_if structure
\param _params parameters to be set
\ingroup IFXUSB_CIF
*/
extern void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params);
/*!
\fn void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if)
\brief This function enables the Host mode interrupts.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if)
\brief This function disables the Host mode interrupts.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if);
#if defined(__IS_TWINPASS__)
extern void ifxusb_enable_afe_oc(void);
#endif
/*!
\fn void ifxusb_vbus_init(ifxusb_core_if_t *_core_if)
\brief This function init the VBUS control.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_vbus_init(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_vbus_free(ifxusb_core_if_t *_core_if)
\brief This function free the VBUS control.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_vbus_free(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_vbus_on(ifxusb_core_if_t *_core_if)
\brief Turn on the USB 5V VBus Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_vbus_on(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_vbus_off(ifxusb_core_if_t *_core_if)
\brief Turn off the USB 5V VBus Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_vbus_off(ifxusb_core_if_t *_core_if);
/*!
\fn int ifxusb_vbus(ifxusb_core_if_t *_core_if)
\brief Read Current VBus status
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern int ifxusb_vbus(ifxusb_core_if_t *_core_if);
#if defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
/*!
\fn void ifxusb_oc_int_on(void)
\brief Turn on the OC interrupt
\ingroup IFXUSB_CIF
*/
extern void ifxusb_oc_int_on(void);
/*!
\fn void ifxusb_oc_int_off(void)
\brief Turn off the OC interrupt
\ingroup IFXUSB_CIF
*/
extern void ifxusb_oc_int_off(void);
#endif //defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef __IS_DEVICE__
/*!
\fn void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if)
\brief This function enables the Device mode interrupts.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if);
/*!
\fn uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if)
\brief Gets the current USB frame number. This is the frame number from the last SOF packet.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in)
\brief Set the EP STALL.
\param _core_if Pointer of core_if structure
\param _epno EP number
\param _is_in 1: is IN transfer
\ingroup IFXUSB_CIF
*/
extern void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in);
/*!
\fn void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in)
\brief Set the EP STALL.
\param _core_if Pointer of core_if structure
\param _epno EP number
\param _ep_type EP Type
\ingroup IFXUSB_CIF
*/
extern void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in);
/*!
\fn void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
\brief This function initializes the IFXUSB controller registers for Device mode.
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
request queues.
This function validate the imported parameters and store the result in the CIF structure.
After
\param _core_if Pointer of core_if structure
\param _params structure of inported parameters
\ingroup IFXUSB_CIF
*/
extern void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params);
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#if defined(__GADGET_LED__) || defined(__HOST_LED__)
/*!
\fn void ifxusb_led_init(ifxusb_core_if_t *_core_if)
\brief This function init the LED control.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_led_init(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_led_free(ifxusb_core_if_t *_core_if)
\brief This function free the LED control.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_led_free(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_led(ifxusb_core_if_t *_core_if)
\brief This function trigger the LED access.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_led(ifxusb_core_if_t *_core_if);
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/* internal routines for debugging */
extern void ifxusb_dump_msg(const u8 *buf, unsigned int length);
extern void ifxusb_dump_spram(ifxusb_core_if_t *_core_if);
extern void ifxusb_dump_registers(ifxusb_core_if_t *_core_if);
extern void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
static inline uint32_t ifxusb_read_core_intr(ifxusb_core_if_t *_core_if)
{
return (ifxusb_rreg(&_core_if->core_global_regs->gintsts) &
(ifxusb_rreg(&_core_if->core_global_regs->gintmsk)
#ifdef __USE_TIMER_4_SOF__
| IFXUSB_SOF_INTR_MASK
#endif
));
}
static inline uint32_t ifxusb_read_otg_intr (ifxusb_core_if_t *_core_if)
{
return (ifxusb_rreg (&_core_if->core_global_regs->gotgint));
}
static inline uint32_t ifxusb_mode(ifxusb_core_if_t *_core_if)
{
return (ifxusb_rreg( &_core_if->core_global_regs->gintsts ) & 0x1);
}
static inline uint8_t ifxusb_is_device_mode(ifxusb_core_if_t *_core_if)
{
return (ifxusb_mode(_core_if) != 1);
}
static inline uint8_t ifxusb_is_host_mode(ifxusb_core_if_t *_core_if)
{
return (ifxusb_mode(_core_if) == 1);
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef __IS_HOST__
static inline uint32_t ifxusb_read_hprt0(ifxusb_core_if_t *_core_if)
{
hprt0_data_t hprt0;
hprt0.d32 = ifxusb_rreg(_core_if->hprt0);
hprt0.b.prtena = 0;
hprt0.b.prtconndet = 0;
hprt0.b.prtenchng = 0;
hprt0.b.prtovrcurrchng = 0;
return hprt0.d32;
}
static inline uint32_t ifxusb_read_host_all_channels_intr (ifxusb_core_if_t *_core_if)
{
return (ifxusb_rreg (&_core_if->host_global_regs->haint));
}
static inline uint32_t ifxusb_read_host_channel_intr (ifxusb_core_if_t *_core_if, int hc_num)
{
return (ifxusb_rreg (&_core_if->hc_regs[hc_num]->hcint));
}
#endif
#ifdef __IS_DEVICE__
static inline uint32_t ifxusb_read_dev_all_in_ep_intr(ifxusb_core_if_t *_core_if)
{
uint32_t v;
v = ifxusb_rreg(&_core_if->dev_global_regs->daint) &
ifxusb_rreg(&_core_if->dev_global_regs->daintmsk);
return (v & 0xffff);
}
static inline uint32_t ifxusb_read_dev_all_out_ep_intr(ifxusb_core_if_t *_core_if)
{
uint32_t v;
v = ifxusb_rreg(&_core_if->dev_global_regs->daint) &
ifxusb_rreg(&_core_if->dev_global_regs->daintmsk);
return ((v & 0xffff0000) >> 16);
}
static inline uint32_t ifxusb_read_dev_in_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num)
{
uint32_t v;
v = ifxusb_rreg(&_core_if->in_ep_regs[_ep_num]->diepint) &
ifxusb_rreg(&_core_if->dev_global_regs->diepmsk);
return v;
}
static inline uint32_t ifxusb_read_dev_out_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num)
{
uint32_t v;
v = ifxusb_rreg(&_core_if->out_ep_regs[_ep_num]->doepint) &
ifxusb_rreg(&_core_if->dev_global_regs->doepmsk);
return v;
}
#endif
extern void ifxusb_attr_create (void *_dev);
extern void ifxusb_attr_remove (void *_dev);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#endif // !defined(__IFXUSB_CIF_H__)

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